Browsing by Author "Yoshida, Naomi"

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration