Browsing by author "Sherazi, Yasser"
Now showing items 1-20 of 32
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A Novel Design Reversible logic based Configurable Fault-Tolerant Embryonic Hardware
Khalil, Kasem; Dey, Bappaditya; Sherazi, Yasser; Kumar, Ashok; Bayoumi, Magdy (2020) -
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Sherazi, Yasser; Chava, Bharani; Debacker, Peter; Garcia Bardon, Marie; Schuddinck, Pieter; Firouzi, Farshad; Raghavan, Praveen; Mercha, Abdelkarim; Verkest, Diederik; Ryckaert, Julien (2016) -
Area and routing efficiency of SWD circuits compared to advanced CMOS
Zografos, Odysseas; Raghavan, Praveen; Sherazi, Yasser; Vaysset, Adrien; Ciubotaru, Florin; Soree, Bart; Lauwereins, Rudy; Radu, Iuliana; Thean, Aaron (2015) -
CFET standard-cell design down to 3Track height for node 3nm and below
Sherazi, Yasser; Chae, Jung Kyu; Debacker, Peter; Mattii, Luca; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Spessot, Alessio; Dounde, Amit; Ryckaert, Julien (2019) -
CMOS area scaling and the need for high aspect ratio vias
Briggs, Basoene; Guissi, Sofiane; Wilson, Chris; Ryckaert, Julien; Paolillo, Sara; Vandersmissen, Kevin; Versluijs, Janko; Lorant, Christophe; Heylen, Nancy; Boemmels, Juergen; Tokei, Zsolt; Sherazi, Yasser; Weckx, Pieter; Kljucar, Luka; van der Veen, Marleen; Boccardi, Guillaume; De Heyn, Vincent; Gupta, Anshul; Ervin, Joseph; Kamon, Matt (2018) -
Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery
Spessot, Alessio; Sharan, Neha; Oh, Hyungrock; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Mallik, Arindam; De Keersgieter, An; Parvais, Bertrand; Sherazi, Yasser; Machkaoutsan, Vladimir; Kim, Cheolgyu; Fazan, Pierre; Mocuta, Dan; Mocuta, Anda; Horiguchi, Naoto (2018-01) -
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Design and pitch scaling for affordable node transition and EUV insertion scenario
Kim, Ryan Ryoung han; Ryckaert, Julien; Raghavan, Praveen; Sherazi, Yasser; Debacker, Peter; Trivkovic, Darko; Gillijns, Werner; Tan, Ling Ee; Drissi, Youssef; Blanco, Victor; Bekaert, Joost; Mao, Ming; Lariviere, Stephane; McIntyre, Greg (2017) -
Design, patterning, and process integration overview for 2nm node
Sherazi, Yasser; Chang, Yi-Han; Drissi, Youssef; Chehab, Bilal; Vega Gonzalez, Victor; Kim, Ryan Ryoung Han; Lee, Jae Uk (2022) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
DTCO exploration for efficient standard cell power rails
Chava, Bharani; Ryckaert, Julien; Mattii, Luca; Sherazi, Yasser; Debacker, Peter; Spessot, Alessio; Verkest, Diederik (2018) -
Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires
Garcia Bardon, Marie; Sherazi, Yasser; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Debacker, Peter; Baert, Rogier; Mertens, Hans; Badaroglu, Mustafa; Mocuta, Anda; Horiguchi, Naoto; Mocuta, Dan; Raghavan, Praveen; Ryckaert, Julien; Verkest, Diederik; Steegen, An (2016) -
IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend
Kim, Ryan Ryoung han; Sherazi, Yasser; Debacker, Peter; Raghavan, Praveen; Ryckaert, Julien; Mallik, Arindam; Verkest, Diederik; Lee, Jae Uk; Gillijns, Werner; Tan, Ling Ee; Blanco, Victor; Ronse, Kurt; McIntyre, Greg (2018) -
Impact of a SADP flow on the design and process for N10/N7 layers
Gillijns, Werner; Sherazi, Yasser; Trivkovic, Darko; Chava, Bharani; Vandewalle, B.; Gerousis, V.; Raghavan, Praveen; Ryckaert, Julien; Mercha, Abdelkarim; Verkest, Diederik; McIntyre, Greg; Ronse, Kurt (2015) -
IR-drop aware design and Technology co-optimization for N5 node with different device and cell height options
Mattii, Luca; Milojevic, Dragomir; Debacker, Peter; Sherazi, Yasser; Berekovic, Mladen; Raghavan, Praveen (2017) -
Low track height standard cell design in iN7 using scaling boosters
Sherazi, Yasser; Jha, Chaitanya; Rodopoulos, Dimitrios; Debacker, Peter; Chava, Bharani; Mattii, Luca; Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Gerousis, V.; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Ryckaert, Julien (2017) -
Low track height standard-cells enable high-placement density and low-BEOL cost
Debacker, Peter; Mattii, Luca; Sherazi, Yasser; Baert, Rogier; Gerousis, Vassilios; Nauts, Claire; Raghavan, Praveen; Ryckaert, Julien; Kim, Ryan Ryoung han; Verkest, Diederik (2017) -
Metal stack optimization for low-power and high-density for N7-N5
Raghavan, Praveen; Firouzi, Farshad; Matti, L.; Debacker, Peter; Baert, Rogier; Sherazi, Yasser; Trivkovic, Darko; Gerousis, V.; Dusa, Mircea; Ryckaert, Julien; Tokei, Zsolt; Verkest, Diederik; McIntyre, Greg; Ronse, Kurt (2016) -
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
Yakimets, Dmitry; Garcia Bardon, Marie; Jang, Doyoung; Schuddinck, Pieter; Sherazi, Yasser; Weckx, Pieter; Miyaguchi, Kenichi; Parvais, Bertrand; Raghavan, Praveen; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017)