Browsing by author "Thangaraju, Sarasvathi"
Now showing items 1-9 of 9
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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Mercha, Abdelkarim; Van der Plas, Geert; Moroz, V.; De Wolf, Ingrid; Asimakopoulos, Panagiotis; Minas, Nikolaos; Domae, Shinichi; Perry, Dan; Choi, M.; Redolfi, Augusto; Okoro, Chukwudi; Yang, Yu; Van Olmen, Jan; Thangaraju, Sarasvathi; Sabuncuoglu Tezcan, Deniz; Soussan, Philippe; Cho, Jong Hoon; Yakovlev, A.; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Mercha, Abdelkarim; Redolfi, Augusto; Stucchi, Michele; Minas, Nikolaos; Van Olmen, Jan; Thangaraju, Sarasvathi; Velenis, Dimitrios; Domae, Shinichi; Yang, Yu; Katti, Guruprasad; Labie, Riet; Okoro, Chukwudi; Zhao, Ming; Asimakopoulos, Panagiotis; De Wolf, Ingrid; Chiarella, Thomas; Schram, Tom; Rohr, Erika; Van Ammel, Annemie; Jourdain, Anne; Ruythooren, Wouter; Armini, Silvia; Radisic, Alex; Philipsen, Harold; Heylen, Nancy; Kostermans, Maarten; Jaenen, Patrick; Sleeckx, Erik; Sabuncuoglu Tezcan, Deniz; Debusschere, Ingrid; Soussan, Philippe; Perry, Dan; Van der Plas, Geert; Cho, Jong Hoon; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers
Redolfi, Augusto; Velenis, Dimitrios; Thangaraju, Sarasvathi; Nolmans, Philip; Jaenen, Patrick; Kostermans, Maarten; Baier, Ulrich; Van Besien, Els; Dekkers, Harold; Witters, Thomas; Jourdan, Nicolas; Van Ammel, Annemie; Vandersmissen, Kevin; Rodet, Simon; Philipsen, Harold; Radisic, Alex; Heylen, Nancy; Travaly, Youssef; Swinnen, Bart; Beyne, Eric (2011-06) -
Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
Jourdain, Anne; Buisson, Thibault; Phommahaxay, Alain; Redolfi, Augusto; Thangaraju, Sarasvathi; Travaly, Youssef; Beyne, Eric; Swinnen, Bart (2011) -
On the thermal stability of physically-vapor-deposited diffusion barriers in 3D through-silicon vias during IC processing
Civale, Yann; Croes, Kristof; Miyamori, Yuichi; Velenis, Dimitrios; Redolfi, Augusto; Thangaraju, Sarasvathi; Van Ammel, Annemie; Cherman, Vladimir; Van der Plas, Geert; Cockburn, Andrew; Gravey, Virginie; Kumar, Nirajan; Cao, Zhitao; Travaly, Youssef; Tokei, Zsolt; Beyne, Eric; Swinnen, Bart (2013) -
Plasma enhanced atomic layer deposition of silicon oxide for through silicon via
Kwon, Hak-Yong; Kim, Jeon-Ho; Kim, Young-Hoon; Kim, Young-Jae; Kim, Dae-Youn; Choi, Seung-Woo; Park, Hyung-Sang; Yoo, Yong-Min; Thangaraju, Sarasvathi; Redolfi, Augusto; Travaly, Youssef; Swinnen, Bart; Beynet, Julien (2010) -
Relationships between deposition parameters, step coverage, throughput, and electrical properties of PEALD SiO2 insulation liners for HVM TSV application
Jung, In Soo; Woo, Jeong-Jun; Kwon, Hak Yong; Kim, Young-Jae; Kang, Dong-Suk; Park, Ju-Hyuk; Ahn, Dae-Young; Choi, Seung-Woo; Park, Hyung-Sang; Yoo, Yong Min; Civale, Yann; Redolfi, Augusto; Thangaraju, Sarasvathi; Travaly, Youssef; Swinnen, Bart; Beyne, Eric; De Roest, David; Beynet, Julien (2011) -
Technology assessment of through-silicon via by using C-V and C-t Measurements
Katti, Guruprasad; Stucchi, Michele; Velenis, Dimitrios; Thangaraju, Sarasvathi; De Meyer, Kristin; Dehaene, Wim; Beyne, Eric (2011) -
Thermal stability of copper through-silicon via barriers during IC processing
Civale, Yann; Croes, Kristof; Miyamori, Yuichi; Thangaraju, Sarasvathi; Redolfi, Augusto; Van Ammel, Annemie; Velenis, Dimitrios; Cherman, Vladimir; Hendrickx, Paul; Van der Plas, Geert; Cockburn, Andrew; Gravey, Virginie; Kumar, Nirajan; Zhitao, Cao; Sabuncuoglu Tezcan, Deniz; Soussan, Philippe; Travaly, Youssef; Tokei, Zsolt; Beyne, Eric; Swinnen, Bart (2011)