Browsing by author "Clark, William"
Now showing items 1-6 of 6
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A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow
Clark, William; Juncker, Aurelie; Paladugu, E.; Fried, David; Wilson, Chris; Pourtois, Geoffrey; Gallagher, Emily; de Jamblinne de Meux, Albert; Piumi, Daniele; Boemmels, Juergen; Tokei, Zsolt; Mocuta, Dan (2016) -
Feasibility study of fully self aligned vias for 5nm node BEOL
Murdoch, Gayle; Boemmels, Juergen; Wilson, Chris; Babaei Gavan, Khashayar; Le, Quoc Toan; Tokei, Zsolt; Clark, William (2017) -
Modeling of tone inversion process flow for N5 interconnect to characterize block tip to tip
Guissi, Sofiane; Clark, William; Juncker, Aurélie; Ervin, J.; Greiner, K.; Fried, D.; Briggs, Basoene; Devriendt, Katia; Sebaai, Farid; Charley, Anne-Laure; Wilson, Chris; Boemmels, Juergen; Tokei, Zsolt (2017) -
RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs
Ragnarsson, Lars-Ake; Dekkers, Harold; Schram, Tom; Chew, Soon Aik; Parvais, Bertrand; Dehan, Morin; Devriendt, Katia; Tao, Zheng; Sebaai, Farid; Baerts, Christina; Van Elshocht, Sven; Yoshida, Naomi; Phatak, Anup; Lazik, Christoph; Brand, Adam; Clark, William; Fried, David; Mocuta, Dan; Barla, Kathy; Horiguchi, Naoto; Thean, Aaron (2015) -
Self-aligned-quadruple-patterning for N7/N5 silicon fins
Altamirano Sanchez, Efrain; Tao, Zheng; Gunay Demirkol, Anil; Lorusso, Gian; Hopf, Toby; Everaert, Jean-Luc; Sobieski, Daniel; Ou, Fung Suong; Hellin, David; Clark, William (2016) -
Toward sub-20nm pitch Fin patterning and integration with DSA
Sayan, Safak; Marzook, Taisir; Chan, BT; Vandenbroeck, Nadia; Singh, Arjun; Laidler, David; Altamirano Sanchez, Efrain; Leray, Philippe; Rincon Delgadillo, Paulina; Gronheid, Roel; Vandenberghe, Geert; Clark, William; Juncker, Aurelie (2016)