Now showing items 1-15 of 15

    • 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices 

      Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019)
    • 300mm IGZO nFETs with low-T Ru contacts for localized doping and increased BEOL compatibility 

      Kljucar, Luka; Smets, Quentin; van Setten, Michiel; Mitard, Jerome; Belmonte, Attilio; Dekkers, Harold; Teugels, Lieve; Mao, Ming; Puliyalil, Harinarayanan; del Agua Borniquel, Jose Ignacio; Delhougne, Romain; Sankaran, Kiroubanand; Tokei, Zsolt (2020)
    • Capacitor-less, Long-Retention (> 400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM 

      Belmonte, Attilio; Oh, Hyungrock; Rassoul, Nouredine; Donadio, Gabriele Luca; Mitard, Jerome; Dekkers, Harold; Delhougne, Romain; Subhechha, Subhali; Vaisman Chasin, Adrian; van Setten, Michiel; Kljucar, Luka; Mao, Ming; Puliyalil, Harinarayanan; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Banerjee, Kaustuv; Souriau, Laurent; Tokei, Zsolt; Goux, Ludovic; Kar, Gouri Sankar (2020)
    • Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control 

      Subhechha, Subhali; Rassoul, Nouredine; Belmonte, Attilio; Hody, Hubert; Dekkers, Harold; van Setten, Michiel; Vaisman Chasin, Adrian; Houshmand Sharifi, Shamin; Banerjee, Kaustuv; Puliyalil, Harinarayanan; Kundu, Souvik; Pak, Murat; Tsvetanova, Diana; Bazzazian, Nina; Vandersmissen, Kevin; Batuk, Dmitry; Geypen, Jef; Heijlen, Jeroen; Delhougne, Romain; Kar, Gouri Sankar (2022)
    • Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below 

      Montero Alvarez, Daniel; Vega Gonzalez, Victor; Feurprier, Yannick; Varela Pedreira, Olalla; Oikawa, Noriaki; Martinez Alanis, Gerardo Tadeo; Batuk, Dmitry; Puliyalil, Harinarayanan; Versluijs, Janko; De Coster, Hanne; Bazzazian, Nina; Jourdan, Nicolas; Kumar, Kaushik; Lazzarino, Frederic; Murdoch, Gayle; Park, Seongho; Tokei, Zsolt (2022-06-29)
    • Etch challenges in high aspect ratio aupervia patterning 

      Puliyalil, Harinarayanan; Feurprier, Yannick; Briggs, Basoene; Lazzarino, Frederic; Wilson, Chris; Kumar, Kaushik (2019)
    • Exploring the use of Tungsten-based Hard Masks in BEOL interconnects for 3nm node and beyond 

      Montero Alvarez, Daniel; Vega Gonzalez, Victor; Puliyalil, Harinarayanan; Nie, Jiuyuan; Yang, Jialing; Schleicher, Filip; Mclaughlin, Kevin; Versluijs, Janko; Lazzarino, Frederic; Park, Seongho; Tokei, Zsolt (2022-11-10)
    • First demonstration of sub-12 nm gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices 

      Subhechha, Subhali; Rassoul, Nouredine; Belmonte, Attilio; Delhougne, Romain; Donadio, Gabriele Luca; Banerjee, Kaustuv; Dekkers, Harold; van Setten, Michiel; Mao, Ming; Puliyalil, Harinarayanan; Kundu, Shreya; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Bazzazian, Nina; Klijs, Lars; Vaisman Chasin, Adrian; Heijlen, Jeroen; Kar, Gouri Sankar (2021)
    • High Aspect Ratio Supervia Dual Damascene etch for iN5 and beyond 

      Puliyalil, Harinarayanan; Feurprier, Yannick; Oikawa, Noriaki; Vega Gonzalez, Victor; Briggs, Basoene; Montero Alvarez, Daniel; Lazzarino, Frederic; Tokei, Zsolt; Satoru, Nakamura; Tahara, Shigeru; Kumar, Kaushik (2021)
    • Interconnects for scaled SRAM with vertical Surrounded Gate Transistors (SGT) 

      Boemmels, Juergen; Harada, N.; Kim, Min-Soo; Mitard, Jerome; Kikuchi, Yoshiaki; Li, Waikin; Tao, Zheng; Puliyalil, Harinarayanan; Devriendt, Katia; Lorant, Christophe; Le, Quoc Toan; Kesters, Els; Jourdan, Nicolas; El-Mekki, Zaid; Teugels, Lieve; van der Veen, Marleen; Li, Y.; Nakamura, H.; Mocuta, Dan; Masuoka, F. (2019)
    • Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations 

      Vega Gonzalez, Victor; Montero Alvarez, Daniel; Versluijs, Janko; Varela Pedreira, Olalla; Jourdan, Nicolas; Puliyalil, Harinarayanan; Chehab, Bilal; Peissker, Tobias; Haider, Ali; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Le, Quoc Toan; Bazzazian, Nina; Heylen, Nancy; van der Veen, Marleen; El-Mekki, Zaid; Webers, Tomas; Vats, H.; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Gillijns, Werner; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Ciofi, Ivan; De Wachter, Bart; Swerts, Johan; Grieten, Eva; Ercken, Monique; Kim, Ryan Ryoung han; Croes, Kristof; Leray, Philippe; Jaysankar, Manoj; Nagesh, Nishanth; Ramakers, Leon; Murdoch, Gayle; Park, Seongho; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)
    • Sub-40mV Sigma-VTH IGZO nFETs in 300mm Fab 

      Mitard, Jerome; Kljucar, Luka; Rassoul, Nouredine; Dekkers, Harold; van Setten, Michiel; Vaisman Chasin, Adrian; Pourtois, Geoffrey; Belmonte, Attilio; Donadio, Gabriele Luca; Goux, Ludovic; Mao, Ming; Puliyalil, Harinarayanan; Teugels, Lieve; Tsvetanova, Diana; Nag, Manoj; Steudel, Soeren; del Agua Borniquel, Jose Ignacio; Ramalingam, Jothilingam; Delhougne, Romain; Wilson, Chris; Tokei, Zsolt; Kar, Gouri Sankar (2020)
    • Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium 

      Vega Gonzalez, Victor; Puliyalil, Harinarayanan; Versluijs, Janko; Lesniewska, Alicja; Varela Pedreira, Olalla; Baert, Rogier; Paolillo, Sara; Decoster, Stefan; Schleicher, Filip; Montero Alvarez, Daniel; Bekaert, Joost; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Teugels, Lieve; Heylen, Nancy; Jourdan, Nicolas; El-Mekki, Zaid; van der Veen, Marleen; Ciofi, Ivan; Briggs, Basoene; Heijlen, Jeroen; Dupas, Luc; De Wachter, Bart; Vancoille, Eric; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Demonie, Ingrid; Lazzarino, Frederic; Ercken, Monique; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Jaysankar, Manoj; Wilson, Chris; Murdoch, Gayle; Tokei, Zsolt (2020)
    • Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10(3)s retention, > 10(11) cycles endurance and L-g scalability down to 14nm 

      Belmonte, Attilio; Oh, Hyungrock; Subhechha, Subhali; Rassoul, Nouredine; Hody, Hubert; Dekkers, Harold; Delhougne, Romain; Ricotti, Lorenzo; Banerjee, Kaustuv; Vaisman Chasin, Adrian; van Setten, Michiel; Puliyalil, Harinarayanan; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Vandersmissen, Kevin; Kundu, Shreya; Heijlen, Jeroen; Batuk, Dmitry; Geypen, Jef; Goux, Ludovic; Kar, Gouri Sankar (2021)
    • Three-layer BEOL process integration with supervia and self-aligned-block options for the 3nm node 

      Vega Gonzalez, Victor; Wilson, Chris; Briggs, Basoene; Decoster, Stefan; Versluijs, Janko; Lesniewska, Alicja; Paolillo, Sara; Baert, Rogier; Puliyalil, Harinarayanan; Bekaert, Joost; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Varela Pedreira, Olalla; Teugels, Lieve; Heylen, Nancy; El-Mekki, Zaid; van der Veen, Marleen; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Jourdan, Nicolas; Ciofi, Ivan; Gupta, Anshul; Contino, Antonino; Boccardi, Guillaume; Lariviere, Stephane; Dupas, Luc; De Wachter, Bart; Vancoille, Eric; Lazzarino, Frederic; Ercken, Monique; Debacker, Peter; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Dillemans, Leander; Chen, Yi-Fan; Tokei, Zsolt (2019)