Browsing by author "Wu, Cheng-Wen"
Now showing items 1-11 of 11
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Automated probe mark analysis
Rong, Yu-Rong; Wu, Cheng-Wen; Fodor, Ferenc; Marinissen, Erik Jan (2018-06) -
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization
Jian, Yu-Rong; Fodor, Ferenc; Wu, Cheng-Wen; Marinissen, Erik Jan (2021) -
DfT architecture for 3D-SICs with multiple towers
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011-05) -
DfT architecture for multi-tower 3D-SICs
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011) -
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages
Chuang, Po-Yao; Lorenzelli, Francesco; Chakravarty, Sreejit; Boutobza, Slimane; Wu, Cheng-Wen; Gielen, Georges; Marinissen, Erik Jan (2023) -
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages
Chuang, Po-Yao; Lorenzelli, Francesco; Chakravarty, Sreejit; Wu, Cheng-Wen; Gielen, Georges; Marinissen, Erik Jan (2023) -
Low-cost post-bond testing of 3D-ICs containing a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2014-11) -
Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep K.; Wu, Cheng-Wen (2011-11) -
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011-09) -
Solutions to multiple probing challenges for test access to multi-die stacked integrated circuits
Marinissen, Erik Jan; Fodor, Ferenc; Podpod, Arnita; Stucchi, Michele; Jian, Yu-Rong; Wu, Cheng-Wen (2018-11) -
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults
Hu, Min-Chun; Gao, Zhan; Malagi, Santosh; Swenton, Joe; Huisken, Jos; Goossens, Kees; Wu, Cheng-Wen; Marinissen, Erik Jan (2020)