Browsing by author "Biesemans, Serge"
Now showing items 21-40 of 237
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Addressing key concerns for implementation of Ni FUSI into manufacturing for 45/32 nm CMOS
Shickova, Adelina; Kauerauf, Thomas; Rothschild, Aude; Aoulaiche, Marc; Sahhaf, Sahar; Kaczer, Ben; Veloso, Anabela; Torregiani, Cristina; Pantisano, Luigi; Lauwers, Anne; Zahid, Mohammed; Rost, Tim; Tigelaar, H.; Pas, M.; Fretwell, J.; McCormack, J.; Hoffmann, Thomas; Kerner, Christoph; Chiarella, Thomas; Brus, Stephan; Harada, Yoshinao; Niwa, Masaaki; Kaushik, Vidya; Maes, Herman; Absil, Philippe; Groeseneken, Guido; Biesemans, Serge; Kittl, Jorge (2007) -
Advanced 2D/3D simulations for laser annealed device using an atomic kinetic monte carlo approach and scanning spreading resistance microscopy (SRRM)
Noda, T.; Eyben, Pierre; Vandervorst, Wilfried; Vrancken, Christa; Rosseel, Erik; Ortolland, Claude; Clarysse, Trudo; Goossens, Jozefien; De Keersgieter, An; Felch, S.; Schreutelkamp, Rob; Absil, Philippe; Jurczak, Gosia; De Meyer, Kristin; Biesemans, Serge; Hoffmann, Thomas Y. (2008) -
Advanced CMOS device technologies for 45nm node and below
Veloso, Anabela; Hoffmann, Thomas; Lauwers, Anne; Yu, HongYu; Severi, Simone; Augendre, Emmanuel; Kubicek, Stefan; Verheyen, Peter; Collaert, Nadine; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2007) -
Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges
Veloso, Anabela; Collaert, Nadine; De Keersgieter, An; Witters, Liesbeth; Rooyackers, Rita; Hoffmann, Thomas; Biesemans, Serge; Jurczak, Gosia (2009) -
Advanced Ni-based FUlly SIlicidation (FUSI) technology for low-Vt CMOS devices
Yu, HongYu; Veloso, Anabela; Lauwers, Anne; Biesemans, Serge (2007) -
ALD high-K and metal gate solutions
Absil, Philippe; Ragnarsson, Lars-Ake; Hoffmann, Thomas Y.; Biesemans, Serge (2009) -
Analysis of As, P diffusion and defect evolution during sub-millisecond non-melt laser annealing based on an atomistic kinetic Monte Carlo approach
Noda, Taiji; Vandervorst, Wilfried; Felch, S.; Parihar, V.; Cuperus, Aldert; Mcintosh, R.; Vrancken, Christa; Rosseel, Erik; Bender, Hugo; Van Daele, Benny; Niwa, Masaaki; Umimoto, H.; Schreutelkamp, Rob; Absil, Philippe; Jurczak, Gosia; De Meyer, Kristin; Biesemans, Serge; Hoffmann, Thomas Y. (2007) -
Analysis of pocket profile deactivation and its impact on Vth variation for laser annealed device using an atomistic kinetic Monte Carlo approach
Noda, Taichi; Vandervorst, Wilfried; Vrancken, Christa; Ortolland, Claude; Rosseel, Erik; Absil, Philippe; Biesemans, Serge; Hoffmann, Thomas Y. (2010) -
Analytical calculation of subthreshold slope increase in short-channel MOSFET's by taking drift component into account
Biesemans, Serge; De Meyer, Kristin (1995) -
Analytical Calculation of the Subthreshold Slope Increase in Short Channel MOSFET's by Taking the Drift Component into Account
Biesemans, Serge; De Meyer, Kristin (1994) -
Analytical Calculations of a Figure of Merit for Novel MOSFET Architectures for the Sub 0.25 mm Range
Biesemans, Serge; Kubicek, Stefan; De Meyer, Kristin (1994) -
Assessment of a MOSFET circuit model as a tool for device design down to 0.05 μm
Biesemans, Serge; De Meyer, Kristin (1997) -
Atomistic understanding of a single gated dopant atom in a MOSFET
Lansbergen, G.; Rahman, R.; Wellard, C.; Caro, J.; Collaert, Nadine; Biesemans, Serge; Klimeck, G.; Hollenberg, L.; Rogge, S. (2008) -
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Chiarella, Thomas; Witters, Liesbeth; Mercha, Abdelkarim; Kerner, Christoph; Rakowski, Michal; Ortolland, Claude; Ragnarsson, Lars-Ake; Parvais, Bertrand; De Keersgieter, An; Kubicek, Stefan; Redolfi, Augusto; Vrancken, Christa; Brus, Stephan; Lauwers, Anne; Absil, Philippe; Biesemans, Serge; Hoffmann, Thomas Y. (2010) -
Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node
Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022) -
Buried Power Rail Metal exploration towards the 1 nm Node
Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020) -
Calibrated PSCAR stochastic simulation
Dinh, Cong Que; Nagahara, Seji; Shiraishi, Gousuke; Minekawa, Yukie; Kamei, Yuya; Carcasi, Michael; Ide, Hiroyuki; Kondo, Yoshihiro; Yoshida, Yuichi; Yoshihara, Kosuke; Shimada, Ryo; Tomono, Masaru; Moriya, Teruhiko; Takeshita, Kazuhiro; Nafus, Kathleen; Biesemans, Serge; Petersen, John; De Simone, Danilo; Foubert, Philippe; De Bisschop, Peter; Vandenberghe, Geert; Stock, Hans-Jurgen; Meliorisz, Balint (2019) -
Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs
Veloso, Anabela; Witters, Liesbeth; Demand, Marc; Ferain, Isabelle; Son, Nak Jin; Kaczer, Ben; Roussel, Philippe; Adelmann, Christoph; Brus, Stephan; Richard, Olivier; Bender, Hugo; Conard, Thierry; Vos, Rita; Rooyackers, Rita; Van Elshocht, Sven; Collaert, Nadine; De Meyer, Kristin; Biesemans, Serge; Jurczak, Malgorzata (2008) -
Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications
Ortolland, Claude; Mathew, Suraj; Duffy, Ray; Saino, Kanta; Kim, Chul Sung; Mertens, Sofie; Horiguchi, Naoto; Vrancken, Christa; Chiarella, Thomas; Kerner, Christoph; Absil, Philippe; Lauwers, Anne; Biesemans, Serge; Hoffmann, Thomas Y. (2009)