Browsing by author "Taouil, Mottaqiallah"
Now showing items 21-40 of 43
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Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
Marinissen, Erik Jan; De Wachter, Bart; Smith, Ken; Kiesewetter, Joerg; Taouil, Mottaqiallah; Hamdioui, Said (2014-10) -
Electrical modeling of STT-MRAM defects
Wu, Lizhou; Taouil, Mottaqiallah; Rao, Siddharth; Marinissen, Erik Jan; Hamdioui, Said (2018-11) -
How significant will be the test cost share for 3D die-to-wafer stacked ICs?
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2011-04) -
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Wu, Lizhou; Rao, Siddharth; Taouil, Mottaqiallah; Marinissen, Erik Jan; Kar, Gouri Sankar; Hamdioui, Said (2020) -
Impact of mid-bond Testing in 3D stacked ICs
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan; Bhawmik, Sudipta (2013-10) -
Impact of partial resistive defects and bias temperature instability on SRAM decoder reliability
Khan, Seyab; Taouil, Mottaqiallah; Hamdioui, Said; Kukner, Halil; Raghavan, Praveen; Catthoor, Francky (2013) -
Impact of various test flows on the cost in 3D D2W stacking
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2010-11) -
Integral impact of BTI and voltage temperature variation on SRAM sense amplifier
Agbo, Innocent; Taouil, Mottaqiallah; Hamdioui, Said; Kukner, H.; Weckx, Pieter; Raghavan, Praveen; Catthoor, Francky (2015) -
Interconnect test for 3D stacked memory-on-logic
Taouil, Mottaqiallah; Masadeh, Mahmoud; Hamdioui, Said; Marinissen, Erik Jan (2014-03) -
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design
Wu, Lizhou; Rao, Siddharth; Taouil, Mottaqiallah; Marinissen, Erik Jan; Kar, Gouri Sankar; Hamdioui, Said (2022-01-04) -
Mitigation of Sense Amplifier Degradation Using Skewed Design
Kraak, Daniel; Taouil, Mottaqiallah; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky (2020) -
On maximizing the compound yield for 3D wafer-to-wafer stacked ICs
Taouil, Mottaqiallah; Hamdioui, Said; Verbree, Jouke; Marinissen, Erik Jan (2010-10) -
On modeling and optimizing Cost in 3D stacked-ICs
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2011-12) -
Pinhole defect characterization and modeling for STT-MRAM testing
Wu, Lizhou; Rao, Siddharth; Cardoso Medeiros, Guilherme; Taouil, Mottaqiallah; Marinissen, Erik Jan; Yasin, Farrukh; Couet, Sebastien; Hamdioui, Said; Kar, Gouri Sankar (2019-05) -
Post-bond interconnect test and diagnosis for 3D memory stacked on logic
Taouil, Mottaqiallah; Masadeh, Mahmoud; Hamdioui, Said; Marinissen, Erik Jan (2015-11) -
Quality versus cost analysis for 3D stacked ICs
Taouil, Mottaqiallah; Hamdioui, Said; Marinissen, Erik Jan (2014-04) -
Quantification of sense amplifier offset voltage degradation due to zero-and run-time variability
Agbo, Innocent; Taouil, Mottaqiallah; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Raghavan, Praveen; Catthoor, Francky; Dehaene, Wim (2016) -
Read path degradation analysis in SRAM
Agbo, Innocent; Taouil, Mottaqiallah; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky; Dehaene, Wim (2016) -
Test cost analysis for 3D die-to-wafer stacking
Taouil, Mottaqiallah; Hamdioui, Said; Beenakker, Kees; Marinissen, Erik Jan (2010-12) -
Test impact on the overall die-to-wafer 3D stacked IC cost
Taouil, Mottaqiallah; Hamdioui, Said; Beenakker, Kees; Marinissen, Erik Jan (2012-02)