Impact of ESD Events on TSV Liner Reliability

Abstract

In this work, 0.7 mu m via-last TSV arrays were pre-stressed with a series of ten 60 V ESD pulses. Their liner reliability performances were subsequently investigated though voltage ramp stresses with various ramp rates to assess the impact of the ESD pre-stress on the dielectric properties. The breakdown voltage and leakage current of pre-stressed structures is unaffected by the ESD events.