Browsing by Author "Bock, Karlheinz"
- Results Per Page
- Sort Options
Publication A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
Proceedings paper1996, Proceedings of 18th Annual Electrical Overstress/Electrostatic Discharge Symposium, 10/09/1996, p.302-315Publication A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress
Journal article1998, Journal of Electrostatics, (42) 4, p.351-381Publication A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.600-603Publication Characterisation of reliability of compound semiconductor devices using electrical pulses
Publication Coulomb-blockade in quantum dot-like GaAs field emission tips
Bock, KarlheinzJournal article1996, Phantoms Newsletter, 12, p.4-6Publication ESD issues in compound semiconductor high frequency devices and circuits
Bock, KarlheinzProceedings paper1997, Electrical Overstress/ Electrostatic Discharge Symposium, 23/09/1997, p.1A-1/01/2012Publication ESD issues in compound semiconductor high-frequency devices and circuits
Bock, KarlheinzJournal article1998, Microelectronics Reliability, (38) 11, p.1781-1793Publication ESD protection methodology for deep-submicron CMOS
Proceedings paper1998, Proceedings of the 9th European Symposium on Reliability of Electron Devices and Failure Physics - ESREF, 5/10/1998, p.997-1007Publication ESD protection methodology for deep-submicron CMOS
Journal article1998, Microelectronics Reliability, (38) 6_8, p.997-1007Publication Influence of device geometry on ESD performance for deep submicron CMOS technology
Proceedings paper1999, Tagungsband 6th ESD-Forum; October 1999; München, Germany., p.83-93Publication Influence of gate length on ESD performance for deep submicron CMOS technology
Proceedings paper1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings - EOS-ESD, 28/09/1999, p.95-104Publication Influence of gate length on ESD-performance for deep submicron CMOS technology
Journal article2001, Microelectronics Reliability, (41) 3, p.375-383Publication Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology
Proceedings paper1997, Electrical Overstress/ Electrostatic Discharge Symposium, 23/09/1997, p.308-315Publication Investigation into socketed CDM (SDM) tester parasitics
Publication Non-uniform triggering of gg-n MOSt investigated by combined emission microscopy and transmission line pulsing
Proceedings paper1998, Proceedings 20th EOS/ESD Symposium, 4/10/1998, p.177-186Publication Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing
Journal article1999, Microelectronics and Reliability, (39) 11, p.1551-1561Publication Process and device design influence on the ESD performance of a fully silicided 0.25mm CMOS technology
Proceedings paper1997, Proceedings of the ESD Forum; Berlin, October 1997., p.129-137Publication Pulsed stress reliability investigations of Schottky diodes and HBTs
Publication Simulation study for the CDM ESD behaviour of the grounded-gate nMOS
Journal article1996, Microelectronics and Reliability, 36, p.1739-1742Publication Temperature profile measurement and failure characterization of ESD protection devices using spectroscopic photon emission microscopy and Raman spectroscopy
Proceedings paper1999, Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis - ISTFA, 14/11/1999, p.69-76