Browsing by Author "Groeseneken, Guido"
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Publication 1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor
Journal article2013-03, Applied Physics Letters, (102) 7, p.73503Publication 15-band spectral envelope function formalism applied to broken gap tunnel field-effect transistors
Proceedings paper2015, International Workshop on Computational Electronics - IWCE, 2/09/2015, p.1-4Publication 200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration
; ; ; Publication 200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration
; ; ; Publication 2D rotational invariant multi subband schroedinger-poisson solver to model nanowire transistors
Meeting abstract2010, 14th International Workshop on Computational Electronics - IWCE, 27/10/2010Publication 6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.70-73Publication A 1.3dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Proceedings paper2002-09, Proceedings European Solid-State Circuit Conference - ESSCIRC, 23/09/2002, p.335-338Publication A 1.6dB NF CMOS LNA for GPS with 3kV HBM ESD-protection
Proceedings paper2002, Proceedings 24th EOS/ESD Symposium, 6/10/2002, p.18-25Publication A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
Journal article2025, IEEE JOURNAL OF SOLID-STATE CIRCUITS, (60) 2, p.615-625Publication A 25ns/byte-programmable low-power SSI flash array with a new low-voltage erase scheme for embedded memory applications
Proceedings paper1995, 14th IEEE Nonvolatile Semiconductor Memory Workshop, 13/08/1995, p.2.2Publication A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Proceedings paper2009, Nanotechnology Workshop, 13/06/2009Publication A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS
Proceedings paper2009, 31st Annual EOS/ESD Symposium, 30/08/2009, p.5A.6Publication A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications
Journal article1994, IEEE Trans. Components, Packaging, and Manufacturing Techn. Part A, (17) 3, p.380-389Publication A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Publication A cautionary note when looking for a truly reconfigurable resistive RAM PUF
Proceedings paper2018, Conference on Cryptographic Hardware and Embedded Systems, 9/09/2018, p.98-117Publication A CMOS circuit for evaluating the NBTI over a wide frequency range
Journal article2009, Microelectronics Reliability, (49) 8, p.885-891Publication A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
Proceedings paper1996, Proceedings of 18th Annual Electrical Overstress/Electrostatic Discharge Symposium, 10/09/1996, p.302-315Publication A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress
Journal article1998, Journal of Electrostatics, (42) 4, p.351-381Publication A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.600-603Publication A compact NBTI model for accurate analog integrated circuit reliability simulation
Proceedings paper2011, European Solid State Device Research Conference - ESSDERC, 12/09/2011, p.147-150