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Browsing by Author "Lin, Vic"

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    Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

    Lin, Dennis  
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    Brammertz, Guy  
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    Sioncke, Sonja
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    Fleischmann, Claudia  
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    Delabie, Annelies  
    Proceedings paper
    2009, IEEE International Electron Device Meeting - IEDM, 7/12/2009, p.327-330
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    Epitaxial Ge on standard STI patterned Si wafers: high quality virtual substrates for Ge pMOS and III/V nMOS

    Loo, Roger  
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    Wang, Gang
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    Souriau, Laurent  
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    Lin, Vic
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    Brammertz, Guy  
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    Caymax, Matty  
    Meeting abstract
    2009, 216th ECS Meeting, 4/10/2009, p.2387
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    Epitaxial Ge on standard STI patterned Si wafers: high quality virtual substrates for Ge pMOS and III/V nMOS

    Loo, Roger  
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    Wang, Gang
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    Souriau, Laurent  
    ;
    Lin, Vic
    ;
    Takeuchi, Shotaro
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    Brammertz, Guy  
    Proceedings paper
    2009, ULSI Process Integration 6, 4/10/2009, p.335-350
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    Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

    Wang, Gang
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    Loo, Roger  
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    Souriau, Laurent  
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    Takeuchi, Shotaro
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    De Jaeger, Brice  
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    Lee, W
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    Caymax, Matty  
    Meeting abstract
    2009, E-MRS Spring Meeting Symposium I: Silicon and Germanium Issues for Future CMOS Devices, 8/06/2009
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    Fabrication of high qualtiy Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

    Wang, Gang
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    Loo, Roger  
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    Takeuchi, Shotaro
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    Souriau, Laurent  
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    Lin, Vic
    ;
    Moussa, Alain  
    ;
    Bender, Hugo  
    Journal article
    2010, Thin Solid Films, (518) 9, p.2538-2541
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    High quality and low cost fabrication of virtual Ge substrates on STI patterned Si wafers

    Loo, Roger  
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    Wang, Gang
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    Mitard, Jerome  
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    De Jaeger, Brice  
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    Takeuchi, Shotaro
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    Eneman, Geert  
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    Lin, Vic
    Proceedings paper
    2009-09, 1st International Workshop on Si based Nano-Electronics and -Photonics (SiNEP-09), 20/09/2009, p.77-78
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    High quality Ge virtual substrates on Si wafers with standard STI patterning

    Loo, Roger  
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    Wang, Gang
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    Souriau, Laurent  
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    Lin, Vic
    ;
    Takeuchi, Shotaro
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    Brammertz, Guy  
    Journal article
    2010, Journal of the Electrochemical Society, (157) 1, p.H13-H21
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    Impact of Epi-Si growth temperature on Ge-pFET performance

    Mitard, Jerome  
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    Martens, Koen  
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    De Jaeger, Brice  
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    Franco, Jacopo  
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    Shea, Chris
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    Plourde, Chelsea
    Proceedings paper
    2009-09, 39th European Solid-State Device Research Conference - ESSDERC, 14/09/2009, p.411-414
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    Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

    Nguyen, Duy
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    Rosseel, Erik  
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    Takeuchi, Shotaro
    ;
    Everaert, Jean-Luc
    ;
    Yang, Lijun
    Meeting abstract
    2009, Abstracts 6th International Conference on Silicon Epitaxy and Heterostructures - ICSI-6, 17/05/2009, p.78-79

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