Browsing by Author "Phatak, Anup"
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Publication Effective work function engineering for aggressively scaled planar and FinFET-based devices with high-k last replacement metal gate technology
; ; ; Proceedings paper2012-09, International Conference on Solid State Devices and Materials - SSDM, 25/09/2012Publication Effective work function engineering for aggressively scaled planar and multi-gate fin field-effect transistor-based devices with high-k last replacement metal gate technology
; ; ; Journal article2013, Japanese Journal of Applied Physics, (52) 4, p.04CA02Publication Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond
Proceedings paper2014, VLSI Technology Symposium, 9/06/2014, p.56-57Publication Process control & integration options of RMG Technology for aggressively scaled devices
Proceedings paper2012, Symposium on VLSI Technology - VLSIT, 12/06/2012, p.33-34Publication RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs
Proceedings paper2015, Symposium on VLSI Technology, 15/06/2015, p.148-149Publication W versus Co–Al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (Sub-)22nm technology nodes
; ; ; ; Journal article2013, Japanese Journal of Applied Physics, (52) 4, p.04CA03Publication W vs. Co-Al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (Sub-)22nm technology nodes
; ; ; ; Proceedings paper2012-09, International Conference on Solid State Devices and Materials - SSDM, 25/09/2012