Browsing by Author "Taouil, Mottaqiallah"
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Publication 3D-COSTAR: A cost model for 3D stacked ICs
Oral presentation2013, Friday Workshop on 3D Integration at Design, Automation and Test in Europe - DATEPublication 3D-COSTAR: A cost model for 3D-SICs
Proceedings paper2012-11, IEEE International Workshop on Testing Three-Dimensional Stacked ICs - 3D-TEST, 8/11/2012Publication 3D-COSTAR: A cost model for 3D-SICs
Proceedings paper2012-12, 3-D Architectures for Semiconductor Integration and Packaging - 3D-ASIP, 12/12/2012Publication 3D-COSTAR: A tool for 2.5D/3D test flow optimization
Proceedings paper2015-10, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TEST, 8/10/2015Publication A Classification of Memory-Centric Computing
Publication A Survey on Memory-centric Computer Architectures
Publication BTI analysis for high performance and low power SRAM sense amplifier designs
Proceedings paper2015, 4th MEDIAN Project Workshop (organised as a DATE 2015 Friday Workshop), 1/03/2015Publication Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Proceedings paper2021, Design, Automation and Test in Europe Conference and Exhibition (DATE), FEB 01-05, 2021, p.1717-1722Publication Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Proceedings paper2020, IEEE International Test Conference (ITC), NOV 03-05, 2020Publication Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs
Journal article2022, IEEE TRANSACTIONS ON COMPUTERS, (71) 9, p.2219-2233Publication Comparative analysis of RD and atomistic trap-based BTI models on SRAM sense amplifier
Proceedings paper2015, 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era - DTIS, 1/03/2015, p.1-6Publication Comparative BTI analysis for various sense amplifier designs
Proceedings paper2016, IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - DDECS, 20/04/2016, p.1-6Publication Comparative BTI impact for SRAM cell and sense amplifier designs
Proceedings paper2015, MEDIAN Finale - Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, 10/11/2015Publication Defect and Fault Modeling Framework for STT-MRAM Testing
Journal article2021, IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, (9) 2, p.707-723Publication Design-for-Test for Intermittent Faults in STT-MRAMs
Proceedings paper2024, IEEE European Test Symposium (ETS), MAY 20-24, 2024Publication Device Aware Diagnosis for Unique Defects in STT-MRAMs
Proceedings paper2023, 32nd IEEE Asian Test Symposium (ATS), OCT 14-17, 2023, p.71-76Publication Device-Aware Test for Back-Hopping Defects in STT-MRAMs
Proceedings paper2023, Design, Automation and Test in Europe Conference and Exhibition (DATE), APR 17-19, 2023Publication Device-aware test: A new test approach towards DPPB
Proceedings paper2019-11, IEEE International Test Conference (ITC) 2019, 12/11/2019, p.1-10
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