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Browsing by Author "Tomasini, P."

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    Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions

    Bargallo Gonzalez, Mireia
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    Thomas, Nicole
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    Simoen, Eddy  
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    Verheyen, Peter  
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    Hikavyy, Andriy  
    Proceedings paper
    2007, Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes 7, 7/10/2007, p.47-53
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    Electrical performance comparison of embedded Si1-xGex source/drain junctions processed in 200 mm and 300 mmEpi-reactors

    Bargallo Gonzalez, Mireia
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    Simoen, Eddy  
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    Hikavyy, Andriy  
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    Verheyen, Peter  
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    Loo, Roger  
    Proceedings paper
    2008, Semiconductor Advances for Future Electronics Workshop - SAFE, 27/11/2008, p.539-543
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    Factors influencing the leakage current in embedded SiGe source/drain junctions

    Simoen, Eddy  
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    Bargallo Gonzalez, Mireia
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    Vissouvanadin Soubaretty, Bertrand
    Journal article
    2008, IEEE Transactions on Electron Devices, (55) 3, p.925-930
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    Impact of the Ge content and the epitaxial thickness on the bandgap shrinkage induced leakage current of recessed Si1-xGex source/drain junctions

    Bargallo Gonzalez, Mireia
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    Simoen, Eddy  
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    Vissouvanadin Soubaretty, Bertrand
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    Thomas, Nicole
    Proceedings paper
    2007, Workshop on Semiconductor Advances for Future Electronics and Sensors - SAFE, 29/11/2007, p.496-200
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    Influence of the highly-doped drain implantation and the window size on defect creation in p/n Si1-xGex source/drain junctions

    Chowdhury, Mohammad Kamruzzaman
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    Vissouvanadin Soubaretty, Bertrand
    Proceedings paper
    2008, Gettering and Defect Engineering in Semiconductor Technology XII, 14/10/2007, p.95-100
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    On the 1/f noise in pMOSFETs with embedded SiGe source/drain

    Simoen, Eddy  
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    Verheyen, Peter  
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    Shickova, Adelina
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    Hikavyy, Andriy  
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    Loo, Roger  
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    Claeys, Cor
    Meeting abstract
    2007, 8th European Workshop on ULtimate Integration of Silicon - ULIS, 15/03/2007, p.75-78
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    Relaxation induced excess leakage current in recessed Si1-xGex source/drain junctions

    Bargallo Gonzalez, Mireia
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    Chowdhury, Mohammad Kamruzzaman
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    Bhouri, Nada
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    Verheyen, Peter  
    Proceedings paper
    2007, Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS 3: New Materials, Processes and Equipment, 6/05/2007, p.389-396
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    SiGe recessed source-drain (RSD) stressors for PMOS: effect of device integration flow and increased Ge content on electrical performance

    Machkaoutsan, Vladimir  
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    Verheyen, Peter  
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    Tomasini, P.
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    Eneman, Geert  
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    Loo, Roger  
    Proceedings paper
    2007, International Conference on Solid State Devices and Materials - SSDM, 18/09/2007

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