Browsing by author "Wu, Zhicheng"
Now showing items 1-20 of 33
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3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Besnard, Guillaume; Radu, Ionut; Vandooren, Anne; Wu, Zhicheng; Franco, Jacopo; Li, Waikin; Arimura, Hiroaki; Mannaert, Geert; Rosseel, Erik; Hikavyy, Andriy; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018-11) -
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018) -
A BSIM-Based Predictive Hot-Carrier Aging Compact Model
Xiang, Yang; Tyaginov, Stanislav; Vandemaele, Michiel; Wu, Zhicheng; Franco, Jacopo; Bury, Erik; Truijen, Brecht; Parvais, Bertrand; Linten, Dimitri; Kaczer, Ben (2021) -
A physics-aware compact modeling framework for transistor aging in the entire bias space
Wu, Zhicheng; Franco, Jacopo; Roussel, Philippe; Tyaginov, Stanislav; Truijen, Brecht; Vandemaele, Michiel; Hellings, Geert; Collaert, Nadine; Groeseneken, Guido; Linten, Dimitri; Kaczer, Ben (2019) -
Accelerated Capture and Emission (ACE) measurement pattern for efficient BTI characterization and modeling
Wu, Zhicheng; Franco, Jacopo; Claes, Dieter; Rzepa, Gerhard; Roussel, Philippe; Collaert, Nadine; Groeseneken, Guido; Linten, Dimitri; Grasser, Tibor; Kaczer, Ben (2019) -
Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
Franco, Jacopo; de Marneffe, Jean-Francois; Vandooren, Anne; Kimura, Yosuke; Nyns, Laura; Wu, Zhicheng; El-Sayed, A-M; Jech, M.; Waldhoer, D.; Claes, Dieter; Arimura, Hiroaki; Ragnarsson, Lars-Ake; Afanas'ev, V.; Stesmans, A.; Horiguchi, Naoto; Linten, Dimitri; Grasser, T.; Kaczer, Ben (2020) -
BTI reliability improvement strategies in low thermal budget gate dtacks for 3D sequential integration
Franco, Jacopo; Wu, Zhicheng; Rzepa, Gerhard; Vandooren, Anne; Arimura, Hiroaki; Ragnarsson, Lars-Ake; Hellings, Geert; Brus, Stephan; Cott, Daire; De Heyn, Vincent; Groeseneken, Guido; Horiguchi, Naoto; Ryckaert, Julien; Collaert, Nadine; Linten, Dimitri; Grasser, Tibor; Kaczer, Ben (2018-12) -
Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Vandooren, Anne; Wu, Zhicheng; Khaled, Ahmad; Franco, Jacopo; Parvais, Bertrand; Li, W.; Witters, Liesbeth; Walke, Amey; Peng, Lan; Rassoul, Nouredine; Matagne, Philippe; Jamieson, Geraldine; Inoue, Fumihiro; Nguyen, B.Y.; Debruyn, Haroen; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Zheng, T.; Radisic, Dunja; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Besnard, G.; Schwarzenbach, W.; Gaudin, G.; Radu, Iuliana; Waldron, Niamh; De Heyn, Vincent; Demuynck, Steven; Boemmels, Juergen; Ryckaert, Julien; Collaert, Nadine; Mocuta, Dan (2019) -
Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy
Wu, Zhicheng; Vaisman Chasin, Adrian; Franco, Jacopo; Subhechha, Subhali; Dekkers, Harold; Yengula Venkata Ramana, Bhuvaneshwari; Belmonte, Attilio; Rassoul, Nouredine; van Setten, Michiel; Afanas'ev, V.; Delhougne, Romain; Kaczer, Ben; Kar, Gouri Sankar (2022) -
Degradation Mapping and Impact of Device Dimension on IGZO TFTs BTI
Rinaudo, Pietro; Vaisman Chasin, Adrian; Franco, Jacopo; Wu, Zhicheng; Subhechha, Subhali; Arutchelvan, Goutham; Eneman, Geert; Yengula Venkata Ramana, Bhuvaneshwari; Rassoul, Nouredine; Delhougne, Romain; Kaczer, Ben; De Wolf, Ingrid; Kar, Gouri Sankar (2023) -
Degradation mapping of IGZO TFTs
Rinaudo, P.; Vaisman Chasin, Adrian; Franco, Jacopo; Wu, Zhicheng; Rassoul, Nouredine; Delhougne, Romain; Kaczer, Ben; De Wolf, Ingrid; Kar, Gouri Sankar (2022) -
Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration
Wu, Zhicheng; Franco, Jacopo; Vandooren, Anne; Roussel, Philippe; Kaczer, Ben; Linten, Dimitri; Collaert, Nadine; Groeseneken, Guido (2021) -
Enhancing the quality of low temperature SiO2 by atomic hydrogen exposure for excellent NBTI reliability
Franco, Jacopo; de Marneffe, Jean-Francois; Vandooren, Anne; Kimura, Yosuke; Nyns, Laura; Wu, Zhicheng; El-Sayed, Al-Moatasem; Jech, Markus; Waldhoer, Dominic; Claes, Dieter; Arimura, Hiroaki; Ragnarsson, Lars-Ake; Afanas'ev, Valeri; Stesmans, Andre; Horiguchi, Naoto; Linten, Dimitri; Grasser, Tibor; Kaczer, Ben (2020) -
External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options
Chen, Wen Chieh; Chen, Shih-Hung; Hellings, Geert; Bury, Erik; Simicic, Marko; Wu, Zhicheng; Van der Plas, Geert; Beyne, Eric; Groeseneken, Guido (2021) -
First demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
Vandooren, Anne; Franco, Jacopo; Wu, Zhicheng; Parvais, Bertrand; Li, Waikin; Walke, Amey; Peng, Lan; Deshpande, Paru; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Zheng, T.; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Mannaert, Geert; Chan, BT; Ritzenthaler, Romain; Mitard, Jerome; Ragnarsson, Lars-Ake; Waldron, Niamh; De Heyn, Vincent; Demuynck, Steven; Boemmels, Juergen; Mocuta, Dan; Ryckaert, Julien; Collaert, Nadine (2018) -
Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices
O'Sullivan, Barry; Ritzenthaler, Romain; Rzepa, G; Wu, Zhicheng; Dentoni Litta, Eugenio; Richard, Olivier; Conard, Thierry; Machkaoutsan, Vladimir; Fazan, Pierre; Kim, Cheolgyu; Franco, Jacopo; Kaczer, Ben; Grasser, T; Spessot, Alessio; Linten, Dimitri; Horiguchi, Naoto (2019) -
Improved PBTI reliability in junction-less nFETs fabricated at low thermal budget for 3D sequential integration
Wu, Zhicheng; Franco, Jacopo; Vandooren, Anne; Kaczer, Ben; Roussel, Philippe; Rzepa, Gerhard; Linten, Dimitri; Groeseneken, Guido (2018) -
Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics
Li, Xiangdong; Posthuma, Niels; Bakeroot, Benoit; Liang, Hu; You, Shuzhen; Wu, Zhicheng; Zhao, Ming; Groeseneken, Guido; Decoutere, Stefaan (2021)