Browsing by author "Pak, Murat"

Capacitor-less, Long-Retention (> 400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

Belmonte, Attilio; Oh, Hyungrock; Rassoul, Nouredine; Donadio, Gabriele Luca; Mitard, Jerome; Dekkers, Harold; Delhougne, Romain; Subhechha, Subhali; Vaisman Chasin, Adrian; van Setten, Michiel; Kljucar, Luka; Mao, Ming; Puliyalil, Harinarayanan; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Banerjee, Kaustuv; Souriau, Laurent; Tokei, Zsolt; Goux, Ludovic; Kar, Gouri Sankar (2020)

Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control

Subhechha, Subhali; Rassoul, Nouredine; Belmonte, Attilio; Hody, Hubert; Dekkers, Harold; van Setten, Michiel; Vaisman Chasin, Adrian; Houshmand Sharifi, Shamin; Banerjee, Kaustuv; Puliyalil, Harinarayanan; Kundu, Souvik; Pak, Murat; Tsvetanova, Diana; Bazzazian, Nina; Vandersmissen, Kevin; Batuk, Dmitry; Geypen, Jef; Heijlen, Jeroen; Delhougne, Romain; Kar, Gouri Sankar (2022)

Ferroelectric FET with Gd-doped HfO2: A Step Towards Better Uniformity and Improved Memory Performance

Ronchi, Nicolo; Ragnarsson, Lars-Ake; Breuil, Laurent; Banerjee, Kaustuv; McMitchell, Sean; O'Sullivan, Barry; Milenin, Alexey; Kundu, Shreya; Pak, Murat; Van den Bosch, Geert; Van Houdt, Jan (2021)

First demonstration of ferroelectric Si:Hf0(2) based 3D FE-FET with trench architecture for dense non-volatile memory application

Banerjee, Kaustuv; Breuil, Laurent; Milenin, Alexey; Pak, Murat; Stiers, Jimmy; McMitchell, Sean; Di Piazza, Luca; Van den Bosch, Geert; Van Houdt, Jan (2021)

First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices

Delhougne, Romain; Arreghini, Antonio; Rosseel, Erik; Hikavyy, Andriy; Vecchio, Emma; Zhang, Liping; Pak, Murat; Nyns, Laura; Raymaekers, Tom; Jossart, Nico; Breuil, Laurent; Vadakupudhu Palayam, Senthil; Tan, ChiLim; Van den Bosch, Geert; Furnemont, Arnaud (2018)

First demonstration of MOVPE In1-xGaxAs macaroni channel for 3-D NAND memory devices

Ramesh, Siva; Vadakupudhu Palayam, Senthil; Rosseel, Erik; Arreghini, Antonio; Kunert, Bernardette; Baryshnikova, Marina; Zhang, Liping; Ong, Patrick; Teugels, Lieve; Pak, Murat; Jossart, Nico; Raymaekers, Tom; Stiers, Jimmy; Van den Bosch, Geert; Furnemont, Arnaud (2019)

First demonstration of sub-12 nm gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices

Subhechha, Subhali; Rassoul, Nouredine; Belmonte, Attilio; Delhougne, Romain; Donadio, Gabriele Luca; Banerjee, Kaustuv; Dekkers, Harold; van Setten, Michiel; Mao, Ming; Puliyalil, Harinarayanan; Kundu, Shreya; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Bazzazian, Nina; Klijs, Lars; Vaisman Chasin, Adrian; Heijlen, Jeroen; Kar, Gouri Sankar (2021)

LCDU optimization of STT-MRAM 50nm pitch MTJ pillars for process window improvement

Pak, Murat; Crotti, Davide; Yasin, Farrukh; Ercken, Monique; Halder, Sandip; De Simone, Danilo; Vanelderen, Pieter; Souriau, Laurent; Hody, Hubert; Kar, Gouri Sankar (2019)

Litho Process Development for Pillars to Enable High Density 4F<SUP>2</SUP> Memory Cells at 34nm Pitch

Pak, Murat; Dauendorffer, A.; Nafus, K.; Das, Arijit; Hasan, Mahmudul; Rincon Delgadillo, Paulina (2023)

Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM

Garello, Kevin; Yasin, Farrukh; Hody, Hubert; Couet, Sebastien; Souriau, Laurent; Houshmand Sharifi, Shamin; Swerts, Johan; Carpenter, Robert; Rao, Siddharth; Kim, Woojin; Wu, Jackson; Vudya Sethu, Kiran Kumar; Pak, Murat; Jossart, Nico; Crotti, Davide; Furnemont, Arnaud; Kar, Gouri Sankar (2019)

Orthogonal Array Pillar Process Development for High Density 4F2 Memory Cells at 40nm Pitch and Beyond

Pak, Murat; Zanders, Wesley; Wong, Patrick; Halder, Sandip; Blanc, Romuald; Souriau, Laurent; Lee, Jeonghoon; Kar, Gouri Sankar (2022)

Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars

Pak, Murat; Zanders, Wesley; Wong, Patrick; Halder, Sandip (2021)

Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10(3)s retention, > 10(11) cycles endurance and L-g scalability down to 14nm

Belmonte, Attilio; Oh, Hyungrock; Subhechha, Subhali; Rassoul, Nouredine; Hody, Hubert; Dekkers, Harold; Delhougne, Romain; Ricotti, Lorenzo; Banerjee, Kaustuv; Vaisman Chasin, Adrian; van Setten, Michiel; Puliyalil, Harinarayanan; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Vandersmissen, Kevin; Kundu, Shreya; Heijlen, Jeroen; Batuk, Dmitry; Geypen, Jef; Goux, Ludovic; Kar, Gouri Sankar (2021)