Browsing by author "Deutsch, Sergej"
Now showing items 1-20 of 21
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3D design-for-test architecture
Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03) -
A 3D-DfT demonstrator
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-05) -
A 3D-DfT demonstrator
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-06) -
Automated design-for-test for 2.5D and 3D SICs
Marinissen, Erik Jan; Konijnenburg, Mario; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Goel, Sandeep K. (2011-09) -
Automation of 3D DfT insertion and interconnect test generation
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011) -
Automation of 3D-DfT insertion
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-11) -
Automation of 3D-DfT insertion
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-09) -
Automation of DfT for 3-D stacked die
Beyne, Eric; Konijnenburg, Mario; Marinissen, Erik Jan; Jensen, Lisa; Deutsch, Sergej; Chikermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Goel, Sandeep (2011) -
Automation of DfT insertion and interconnect test generation for 3D stacked ICs
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Konijnenburg, Mario; Marinissen, Erik Jan (2011-05) -
Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014) -
Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-05) -
DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Sood, Navdeep; Marinissen, Erik Jan (2012-05) -
DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks
Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Sood, Navdeep; Goel, Sandeep K.; Chen, Ji-Jan; Mehta, Ashok; Lee, Frank; Marinissen, Erik Jan (2012-11) -
DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM
Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K.; Marinissen, Erik Jan (2012-05) -
Imec's 3D-DfT architecture: basics, extensions, and demonstrator results
Marinissen, Erik Jan; De Wachter, Bart; O'Loughlin, Stephen; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias (2014-06) -
Implementation aspects of a 3D DfT architecture
Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan (2011) -
Interconnect test for wide-IO memory-on-logic stacks
Marinissen, Erik Jan; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhashish; Sood, Navdeep (2012-07) -
Optimization of test-access architecture and test scheduling for 3D ICs
Deutsch, Sergej; Noia, Brandon; Chakrabarty, Krishnendu; Marinissen, Erik Jan (2019-03) -
Robust optimization of test-access architectures under realistic scenarios
Deutsch, Sergej; Chakrabarty, Krishnendu; Marinissen, Erik Jan (2015-11) -
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
Deutsch, Sergej; Chakrabarty, Krishnendu; Marinissen, Erik Jan (2013-09)