Browsing by author "Matagne, Philippe"
Now showing items 1-20 of 66
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12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
A Scalable One Dimensional Silicon Qubit Array with Nanomagnets
Simion, George; Mohiyaddin, Fahd Ayyalil; Li, Roy; Shehata, Mohamed; Dumoulin Stuyck, Nard; Elsayed, Asser; Ciubotaru, Florin; Kubicek, Stefan; Jussot, Julien; Chan, BT; Ivanov, Tsvetan; Godfrin, Clement; Spessot, Alessio; Matagne, Philippe; Govoreanu, Bogdan; Radu, Iuliana (2020) -
Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
Eyben, Pierre; Matagne, Philippe; Chiarella, Thomas; De Keersgieter, An; Kubicek, Stefan; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto; Thean, Aaron; Mocuta, Dan (2016) -
Advances on doping strategies for triple-gate FinFETs and lateral gate-all-around nanowire FETs and their impact on device performance
Veloso, Anabela; De Keersgieter, An; Matagne, Philippe; Horiguchi, Naoto; Collaert, Nadine (2017) -
Benchmarking time-dependent variability of junctionless nanowire FETs
Kaczer, Ben; Rzepa, G.; Franco, Jacopo; Weckx, Pieter; Vaisman Chasin, Adrian; Putcha, Vamsi; Bury, Erik; Simicic, Marko; Roussel, Philippe; Hellings, Geert; Veloso, Anabela; Matagne, Philippe; Grasser, T.; Linten, Dimitri (2017) -
Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Vandooren, Anne; Wu, Zhicheng; Khaled, Ahmad; Franco, Jacopo; Parvais, Bertrand; Li, W.; Witters, Liesbeth; Walke, Amey; Peng, Lan; Rassoul, Nouredine; Matagne, Philippe; Jamieson, Geraldine; Inoue, Fumihiro; Nguyen, B.Y.; Debruyn, Haroen; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Zheng, T.; Radisic, Dunja; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Besnard, G.; Schwarzenbach, W.; Gaudin, G.; Radu, Iuliana; Waldron, Niamh; De Heyn, Vincent; Demuynck, Steven; Boemmels, Juergen; Ryckaert, Julien; Collaert, Nadine; Mocuta, Dan (2019) -
Challenges and opportunities for vertical nanowire FETs: device design and fabrication
Veloso, Anabela; Matagne, Philippe; Huynh Bao, Trong; Eneman, Geert; Loo, Roger; Wostyn, Kurt; Brus, Stephan; Boemmels, Juergen; Mocuta, Dan; Ryckaert, Julien (2018) -
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Veloso, Anabela; Huynh Bao, Trong; Rosseel, Erik; Paraschiv, Vasile; Devriendt, Katia; Vecchio, Emma; Delvaux, Christie; Chan, BT; Ercken, Monique; Tao, Zheng; Li, Waikin; Altamirano Sanchez, Efrain; Versluijs, Janko; Brus, Stephan; Matagne, Philippe; Waldron, Niamh; Ryckaert, Julien; Mocuta, Dan; Collaert, Nadine (2016) -
Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh Bao, Trong; Eneman, Geert; Hellings, Geert; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017) -
Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs
Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017) -
Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology
Gaddemane, Gautam; Bhuwalka, Krishna K.; Matagne, Philippe; Rzepa, Gerhard; Van de Put, Maarten; Santermans, Sybren; Baumgartner, Oskar; Wu, Hao; Hellings, Geert (2022) -
Combining TCAD and advanced metrology techniques to support device integration towards N3
Eyben, Pierre; De Keersgieter, An; Celano, Umberto; Wouters, Lennaert; Chiarella, Thomas; Ritzenthaler, Romain; Mertens, Hans; Richard, Olivier; Paredis, Kristof; Matagne, Philippe; Mitard, Jerome; Horiguchi, Naoto; Goux, Ludovic (2021) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM
Matagne, Philippe; Nakamura, H.; Kim, Min-Soo; Kikuchi, Yoshiaki; Huynh Bao, Trong; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Boemmels, Juergen; Mallik, Arindam; Altamirano Sanchez, Efrain; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Porret, Clément; Mocuta, Dan; Harada, N.; Matsuoka, F. (2018) -
DTCO flow for device exploration
Yakimets, Dmitry; Schuddinck, Pieter; Matagne, Philippe; Parvais, Bertrand; Mocuta, Anda (2018) -
Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node
Liu, Hsiao-Hsuan; Salahuddin, Shairfe Muhammad; Abdi, Dawit; Chen, Rongmei; Weckx, Pieter; Matagne, Philippe; Catthoor, Francky (2022) -
FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)
Tao, Zheng; Li, Waikin; Kim, Min-Soo; Devriendt, Katia; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Matagne, Philippe; Ragnarsson, Lars-Ake; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Altamirano Sanchez, Efrain; Lee, James; Li, YiSuo; Kanazawa, Kenichi; Harada, Nozomu; Masuoka, Fujio (2019) -
Gate-All-Around nanosheet field-effect transistors for advanced logic and memory applications: integration and device features
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Mertens, Hans; Vaisman Chasin, Adrian; Simoen, Eddy; Horiguchi, Naoto (2020) -
Gate-All-Around nanosheet field-effect transistors for advanced logic and memory applications: integration and device features
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Mertens, Hans; Vaisman Chasin, Adrian; Simoen, Eddy; Horiguchi, Naoto (2020)