Browsing by author "Karageorgos, Ioannis"
Now showing items 1-17 of 17
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Density-balancing mask sssignment for via patterning with directed self-assembly
Tung, Maryann C.; Guo, Daifeng; Karageorgos, Ioannis; Wong, Martin D. F.; Wong, H.-S. Philip (2016-10) -
Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits
Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Croes, Kris; Bekaert, Joost; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016-11) -
Design method for the integration of DSA via patterning in sub-7 nm circuits
Karageorgos, Ioannis; Ryckaert, Julien; Croes, Kris; Tung, C. Maryann; Wong, H. -S. Philip; Karageorgos, Evangelos; Gronheid, Roel; Bekaert, Joost; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016) -
Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Karageorgos, Ioannis; Ryckaert, Julien; Tung, C. Maryann; Wong, H.-S. Philip; Gronheid, Roel; Bekaert, Joost; Croes, Kris; Karageorgos, Evangelos; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016) -
Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)
Tung, C. Maryann; Doise, Jan; Karageorgos, Ioannis; Ryckaert, Julien; Wong, H.-S. Philip (2016) -
Design strategy for the integration of DSA vias in sub-7nm interconnects
Karageorgos, Ioannis (2016) -
EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes
Gronheid, Roel; Boeckx, Carolien; Doise, Jan; Bekaert, Joost; Karageorgos, Ioannis; Ryckaert, Julien; Chan, BT; Li, Chenxi; Zou, Yi (2016) -
Feasibility study of grapho-epitaxy DSA for complementing EUV lithography beyond N10
Lin, Chenxi; Zou, Yi; Ambesi, Davide; Druzhinina, Tamara; Wuister, Sander; Karageorgos, Ioannis; Ryckaert, Julien; Raghavan, Praveen; Gronheid, Roel (2015) -
Impact of DSA process variability on circuit performance
Karageorgos, Ioannis; Doise, Jan; Rincon Delgadillo, Paulina; Stucchi, Michele; Baert, Rogier; Gronheid, Roel; Ryckaert, Julien; Vandenberghe, Geert; Dehaene, Wim (2016-10) -
Impact of Interconnect Advanced Patterning Options on Circuit Design
Karageorgos, Ioannis (2017-06) -
Impact of interconnect multiple-patterning variability on SRAMs
Karageorgos, Ioannis; Dehaene, Wim; Stucchi, Michele; Raghavan, Praveen; Ryckaert, Julien; Tokei, Zsolt; Verkest, Diederik; Baert, Rogier; Sakhare, Sushil (2015) -
Implementation of DSA for electrical test vehicles at the 7 nm node
Gronheid, Roel; Doise, Jan; Bekaert, Joost; Chan, BT; Rincon Delgadillo, Paulina; Karageorgos, Ioannis; Ryckaert, Julien; Vandenberghe, Geert; Sayan, Safak; Lin, Guanyang (2015) -
Implementation of templated DSA for via layer patterning at the 7 nm node
Gronheid, Roel; Doise, Jan; Bekaert, Joost; Chan, BT; Karageorgos, Ioannis; Ryckaert, Julien; Vandenberghe, Geert; Cao, Yi; Lin, G.; Somervell, Mark; Fenger, Germain; Fuchimoto, Daisuke (2015) -
Integration of Directed Self-Assembly (DSA) via patterning in sub-7nm interconnects - A designer's perspective
Karageorgos, Ioannis; Dehaene, Wim; Ryckaert, Julien (2016) -
Integration of DSA Via Patterning in sub-7 nm Circuits
Karageorgos, Ioannis; Dehaene, Wim (2016) -
Opportunities and challenges for DSA in logic and memory
Gronheid, Roel; Singh, Arjun; Doise, Jan; Boeckx, Carolien; Karageorgos, Ioannis; Ryckaert, Julien; Pathangi Sriraman, Hari; Rincon Delgadillo, Paulina; Chan, BT; Vandenberghe, Geert (2016) -
Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition
Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Bekaert, Joost; Vandenberghe, Geert; Dehaene, Wim (2016-10)