Browsing by author "Yakimets, Dmitry"
Now showing items 21-40 of 44
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Holisitic device exploration for 7nm node
Raghavan, Praveen; Garcia Bardon, Marie; Jang, Doyoung; Schuddinck, Pieter; Yakimets, Dmitry; Ryckaert, Julien; Mercha, Abdelkarim; Horiguchi, Naoto; Collaert, Nadine; Mocuta, Anda; Mocuta, Dan; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Steegen, An (2015) -
Insights and opportunities for junctionless gate-all-around lateral and vertical nanowire FETs
Veloso, Anabela; Matagne, Philippe; Simoen, Eddy; Vaisman Chasin, Adrian; Kaczer, Ben; Yakimets, Dmitry; Mocuta, Dan; Collaert, Nadine (2017) -
Junctionless versus inversion-mode lateral semiconductor nanowire transistors
Veloso, Anabela; Matagne, Philippe; Simoen, Eddy; Kaczer, Ben; Eneman, Geert; Mertens, Hans; Yakimets, Dmitry; Parvais, Bertrand; Mocuta, Dan (2018) -
Lateral NWFET optimization for beyond 7nm nodes
Yakimets, Dmitry; Jang, Doyoung; Raghavan, Praveen; Eneman, Geert; Mertens, Hans; Schuddinck, Pieter; Mallik, Arindam; Garcia Bardon, Marie; Collaert, Nadine; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; De Meyer, Kristin (2015) -
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
Yakimets, Dmitry; Huynh Bao, Trong; Garcia Bardon, Marie; Dehan, Morin; Collaert, Nadine; Mercha, Abdelkarim; Tokei, Zsolt; Thean, Aaron; Verkest, Diederik; De Meyer, Kristin (2014) -
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
Garcia Bardon, Marie; Moroz, Victor; Eneman, Geert; Schuddinck, Pieter; Dehan, Morin; Yakimets, Dmitry; Jang, Doyoung; Van der Plas, Geert; Mercha, Abdelkarim; Thean, Aaron; Verkest, Diederik; Steegen, An (2013) -
Limitations on lateral nanowire scaling beyond 7nm node
Kumar Das, Uttam; Garcia Bardon, Marie; Jang, Doyoung; Eneman, Geert; Schuddinck, Pieter; Yakimets, Dmitry; Raghavan, Praveen; Groeseneken, Guido (2017) -
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
Weckx, Pieter; Ryckaert, Julien; Dentoni Litta, Eugenio; Yakimets, Dmitry; Matagne, Philippe; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Baert, Rogier; Gupta, Mohit; Oniki, Yusuke; Ragnarsson, Lars-Ake; Horiguchi, Naoto; Spessot, Alessio; Verkest, Diederik (2019) -
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
Yakimets, Dmitry; Garcia Bardon, Marie; Jang, Doyoung; Schuddinck, Pieter; Sherazi, Yasser; Weckx, Pieter; Miyaguchi, Kenichi; Parvais, Bertrand; Raghavan, Praveen; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells
Garcia Bardon, Marie; Sherazi, Yasser; Jang, Doyoung; Yakimets, Dmitry; Schuddinck, Pieter; Baert, Rogier; Mertens, Hans; Mattii, Luca; Parvais, Bertrand; Mocuta, Anda; Verkest, Diederik (2018) -
Process-induced power-performance variability in sub-5nm III-V tunnel FETs
Xiang, Yang; Verhulst, Anne; Yakimets, Dmitry; Parvais, Bertrand; Mocuta, Anda; Groeseneken, Guido (2019-04) -
Sensitivity study of the parasitics of advanced finFETs
Schuddinck, Pieter; Iverson, Ralph; Annamalai, Senthil; Yakimets, Dmitry; Parvais, Bertrand; Sundaresan, Krishnakumar; Mocuta, Anda (2018) -
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
Weckx, Pieter; Ryckaert, Julien; Putcha, Vamsi; De Keersgieter, An; Boemmels, Juergen; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Garcia Bardon, Marie; Ragnarsson, Lars-Ake; Raghavan, Praveen; Kim, Ryan Ryoung han; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
STI and eSiGe source/drain stressors induced stress modeling in 28 nm technology with replacement gate (RMG) process
Jang, Doyoung; Garcia Bardon, Marie; Yakimets, Dmitry; Miyaguchi, Kenichi; De Keersgieter, An; Chiarella, Thomas; Ritzenthaler, Romain; Dehan, Morin; Mercha, Abdelkarim (2013) -
Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node
Pan, Chenyun; Raghavan, Praveen; Yakimets, Dmitry; Debacker, Peter; Catthoor, Francky; Collaert, Nadine; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Naeemi, Azad (2015) -
The impact of sequential-3D integration on semiconductor scaling roadmap
Mallik, Arindam; Vandooren, Anne; Witters, Liesbeth; Walke, Amey; Franco, Jacopo; Sherazi, Yasser; Weckx, Pieter; Yakimets, Dmitry; Garcia Bardon, Marie; Parvais, Bertrand; Debacker, Peter; Ku, B.W.; Lim, S.K.; Mocuta, Anda; Mocuta, Dan; Ryckaert, Julien; Collaert, Nadine; Raghavan, Praveen (2017) -
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
Xiang, Yang; Yakimets, Dmitry; Sant, Saurabh; Memisevic, Elvedin; Garcia Bardon, Marie; Verhulst, Anne; Parvais, Bertrand; Schenk, Andreas; Wernersson, Lars-Erik; Groeseneken, Guido (2018-10) -
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
Hills, Gage; Garcia Bardon, Marie; Doornbos, Gerben; Yakimets, Dmitry; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Mattii, Luca; Sherazi, Yasser; Rodopoulos, Dimitrios; Ritzenthaler, Romain; Lee, Chi-Shuen; Thean, Aaron; Radu, Iuliana; Spessot, Alessio; Debacker, Peter; Catthoor, Francky; Raghavan, Praveen; Shulaker, Max M.; Wong, H.-S. Philip; Mitra, Subhasish (2018) -
Vertical device architecture for 5nm and beyond: device & circuit implications
Thean, Aaron; Yakimets, Dmitry; Huynh Bao, Trong; Schuddinck, Pieter; Sakhare, Sushil; Garcia Bardon, Marie; Sibaja-Hernandez, Arturo; Ciofi, Ivan; Eneman, Geert; Veloso, Anabela; Ryckaert, Julien; Raghavan, Praveen; Mercha, Abdelkarim; Mocuta, Anda; Tokei, Zsolt; Verkest, Diederik; Wambacq, Piet; De Meyer, Kristin; Collaert, Nadine (2015) -
Vertical devices for future nano-electronic applications
Collaert, Nadine; Veloso, Anabela; Huynh Bao, Trong; Yakimets, Dmitry; Ivanov, Tsvetan; Ramesh, Siva; Matagne, Philippe; Sibaja-Hernandez, Arturo; Liu, Ziyang; Merckling, Clement; Waldron, Niamh; Thean, Aaron (2016)