Study of EUV stochastic defect on wafer yield

Abstract

As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do not account for the stochastic-driven defects that changes by both pitches and critical dimensions (CD) in EUV lithography. In this study, a novel approach that incorporates EUV stochastics into the yield modeling, using calibrated stochastic defects from wafer data is introduced. Then a comparative analysis of yield for various EUV insertion scenarios is meticulously performed. Additionally, strategies to enhance yield in EUV lithography, including CD retargeting are proposed.