Repository logo Institutional repository
  • Communities & Collections
  • Browse
  • Site
Search repository
High contrast
  1. Home
  2. Browse by Author

Browsing by Author "Dachs, Charles"

Filter results by typing the first few letters
Now showing 1 - 14 of 14
  • Results Per Page
  • Sort Options
  • Loading...
    Thumbnail Image
    Publication

    45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm

    Henson, Kirklen
    ;
    Lander, Rob
    ;
    Demand, Marc  
    ;
    Dachs, Charles
    ;
    Kaczer, Ben  
    ;
    Deweerd, Wim
    ;
    Schram, Tom  
    Proceedings paper
    2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.851-854
  • Loading...
    Thumbnail Image
    Publication

    A manufacturable 25nm planar MOSFET technology

    Ponomarev, Youri
    ;
    Loo, Josine
    ;
    Dachs, Charles
    ;
    Cubaynes, Florence
    ;
    Verheijen, M. A.
    ;
    Kaiser, M.
    Proceedings paper
    2001, Symposium on VLSI Technology Digest of Technical Papers;, p.33-34
  • Loading...
    Thumbnail Image
    Publication

    A practical baseline process for advanced CMOS devices research

    Ponomarev, Youri
    ;
    Loo, Josine
    ;
    Rittersma, Chris
    ;
    Lander, Rob
    ;
    Hooker, Jacob
    ;
    Doornbos, Gerben  
    Proceedings paper
    2003, Proceedings 33rd European Solid-State Device Research Conference - ESSDERC, 16/09/2003, p.27-30
  • Loading...
    Thumbnail Image
    Publication

    CMOS device optimisation for mixed-signal technologies

    Stolk, Peter
    ;
    Tuinhout, Hans
    ;
    Duffy, Ray
    ;
    Augendre, Emmanuel
    ;
    Bellefroid, L. P.
    ;
    Bolt, M. J. B.
    Proceedings paper
    2001, IEDM Technical Digest, 2/12/2001, p.215-218
  • Loading...
    Thumbnail Image
    Publication

    CMOS integration results for the 90nm technology node

    Jurczak, Gosia  
    ;
    Augendre, Emmanuel
    ;
    Van Bavel, Mieke  
    ;
    Dachs, Charles
    Journal article
    2003, Semiconductor Fabtech, 18, p.129-132
  • Loading...
    Thumbnail Image
    Publication

    CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges

    Dachs, Charles
    ;
    Surdeanu, Radu
    ;
    Pawlak, Bartek  
    ;
    Doornbos, Gerben  
    ;
    Duffy, R.
    ;
    Heringa, Anco
    Proceedings paper
    2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.15-22
  • Loading...
    Thumbnail Image
    Publication

    Gate dielectrics for high performance and low power CMOS SoC applications

    Cubaynes, Florence
    ;
    Dachs, Charles
    ;
    Detcheverry, Celine
    ;
    Zegers, A.
    ;
    Venezia, Vincent
    Proceedings paper
    2002, ESSDERC - 32nd European Solid-State Device Research Conference, 24/09/2002, p.427-430
  • Loading...
    Thumbnail Image
    Publication

    Laser annealing for ultra-shallow junction formation in advanced CMOS

    Surdeanu, Radu
    ;
    Ponomarev, Youri
    ;
    Cerutti, R.
    ;
    Pawlak, Bartek  
    ;
    Nanver, L.K.
    ;
    Hoflijk, Ilse  
    Proceedings paper
    2002, Rapid Thermal And Other Short-Time Processing Technologies III, 12/05/2002, p.413-426
  • Loading...
    Thumbnail Image
    Publication

    Pre-amorphization and co-implantation suitability for advanced PMOS devices integration

    Surdeanu, Radu
    ;
    Pawlak, Bartek  
    ;
    Lindsay, Richard
    ;
    Van Dal, Mark  
    ;
    Doornbos, Gerben  
    ;
    Dachs, Charles
    Proceedings paper
    2003, Extended Abstracts of the 2003 International Conference on Solid State Device and Materials, 16/09/2003, p.740-741
  • Loading...
    Thumbnail Image
    Publication

    RPN oxynitride gate dielectrics for 90nm low power CMOS applications

    Veloso, Anabela  
    ;
    Jurczak, Gosia  
    ;
    Cubaynes, Florence
    ;
    Rooyackers, Rita
    ;
    Mertens, Sofie  
    Proceedings paper
    2002, ESSDERC - 32nd European Solid-State Device Research Conference, 24/09/2002, p.159-162
  • Loading...
    Thumbnail Image
    Publication

    Shallow junctions for sub-100 nm CMOS technology

    Meyssen, Veerle
    ;
    Stolk, Peter
    ;
    van Zijl, Jeroen
    ;
    van Berkum, Jurgen
    ;
    van de Wijgert, Willem
    Proceedings paper
    2001, Si Front-End Processing - Physics and Technology of Dopant-Defect Interactions III, 17/04/2001, p.J.3.5.1-J3.5.6
  • Loading...
    Thumbnail Image
    Publication

    Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

    Jurczak, Gosia  
    ;
    Rooyackers, Rita
    ;
    De Keersgieter, An  
    ;
    Kunnen, Eddy
    ;
    Henson, Kirklen
    Proceedings paper
    2004-09, Proceedings of the 34th European Solid-State Device Research Conference - ESSDERC, 21/09/2004, p.145-148
  • Loading...
    Thumbnail Image
    Publication

    Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

    Veloso, Anabela  
    ;
    Cubaynes, Florence
    ;
    Rothschild, Aude
    ;
    Mertens, Sofie  
    ;
    Degraeve, Robin  
    Proceedings paper
    2003, 33rd European Solid-State Devices Research Conference - ESSDERC, 16/09/2003
  • Loading...
    Thumbnail Image
    Publication

    Ultrashallow junctions for advanced CMOS technology

    Stolk, Peter
    ;
    Meyssen, Veerle
    ;
    Lindsay, Richard
    ;
    Dachs, Charles
    ;
    Mannino, Giovanni
    ;
    Cowern, Nick
    Proceedings paper
    2001, Proceedings SEMI Front End Technology Conference, 24/04/2001

Follow imec on

VimeoLinkedInFacebook

The repository

  • Contact us
  • Policy
  • About imec
Privacy statement | Cookie settings