Browsing by Author "Deutsch, Sergej"
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Publication A 3D-DfT demonstrator
Proceedings paper2014-06, Design Automation Conference - DAC, 1/06/2014Publication A 3D-DfT demonstrator
Proceedings paper2014-05, IEEE North-Atlantic Test Workshop, 14/05/2014Publication Automated design-for-test for 2.5D and 3D SICs
Journal article2011-09, Chip Scale Review, (?) 5, p.18-22Publication Automation of 3D DfT insertion and interconnect test generation
Oral presentation2011, IEEE International Test Conference - ITCPublication Automation of 3D-DfT insertion
Proceedings paper2011-11, IEEE Asian Test Symposium - ATS, 21/11/2011Publication Automation of 3D-DfT insertion
Proceedings paper2011-09, IEEE International Workshop on Testing Three-Dimensional Stacked ICs- 3D-TEST, 22/09/2011Publication Automation of DfT for 3-D stacked die
Proceedings paper2011, 3-D Architectures for Semiconductor Integration and Packaging, 3-D ASIP, 12/12/2011Publication Automation of DfT insertion and interconnect test generation for 3D stacked ICs
Proceedings paper2011-05, IEEE North-Atlantic Test Workshop - NATW, 11/05/2011Publication Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Oral presentation2014, Design, Automation, and Test in Europe - DATE': Friday Workshop on 3D IntegrationPublication Design, test generation, processing, and pre- and post-bond measurement results of a 3D-DfT demonstrator chip stack
Proceedings paper2014-05, CDN Live! EMEA, 19/05/2014Publication DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
Publication DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks
Publication DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM
Proceedings paper2012-05, IEEE North-Atlantic Test Workshop - NATW, 9/05/2012Publication Imec's 3D-DfT architecture: basics, extensions, and demonstrator results
Proceedings paper2014-06, Workshop on Design for 3D Silicon Integration - D43D, 23/06/2014Publication Implementation aspects of a 3D DfT architecture
Oral presentation2011, CDNLive! EMEA (Cadence Design Systems)Publication Interconnect test for wide-IO memory-on-logic stacks
Journal article2012-07, Future Fab International, 42, p.112-117Publication Robust optimization of test-access architectures under realistic scenarios
Journal article2015-11, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), (34) 11, p.1873-1884Publication Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
Proceedings paper2013-09, IEEE International Test Conference - ITC, 10/09/2013, p.7.1