Browsing by Author "Jourdain, Anne"

0-Level packaging techniques for flip-chip mounted MMICs

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

3D backside integration of FinFETs: Is there an impact on LF noise?

3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps

3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers

3D interconnects for quantum computing

3D stacked IC demonstration using a through silicon via first approach

3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)

3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding

3D stacking using bump-less process for sub 10μm pitches

3D stacking using Cu-Cu direct bonding

A 60GHz silicon micromachined cavity resonator with integrated tuning MEMS array

A method to evaluate internal cavity pressure of sealed MEMS devices

Advances in thin wafer debonding and ultra thin 28nm FinFET substrate transfer

Anomalous C-V inversion in TSV's: The problem and its cure

Assessment of the feasibility of 'multiple chips-to-wafer' thermo-compression bonding using FEM

Backside power delivery as a scaling knob for future systems

Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias

BCB collective bonding for 3D stacking

Block level and package level thermal assessment for back side power delivery network.