Browsing by Author "Lander, Rob"
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Publication 45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm
;Henson, Kirklen ;Lander, Rob; ;Dachs, Charles; ;Deweerd, WimProceedings paper2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.851-854Publication A practical baseline process for advanced CMOS devices research
Proceedings paper2003, Proceedings 33rd European Solid-State Device Research Conference - ESSDERC, 16/09/2003, p.27-30Publication Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges
Proceedings paper2009, Silicon-on-Insulator Technology and Devices 14, 24/05/2009, p.45-54Publication ALD deposition of high-k and metal gate stacks for advanced CMOS applications
Proceedings paper2004, Atomic Layer Deposition Conference, 16/08/2004Publication Application of HCl etch in the production of novel devices
Meeting abstract2008, 213th ECS Meeting, 18/05/2008, p.647Publication Application of HCl gas phase etch in the production of novel devices
Proceedings paper2008-05, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS. 4: New Materials, Processes, and Equipment, 18/05/2008, p.329-335Publication Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices
Proceedings paper2008, IEEE International Electron Devices Meeting - IEDM, 15/12/2008, p.535-538Publication Characteristics and integration challenges of FinFET-based devices for (Sub-)22nm technology nodes circuit applications
Proceedings paper2009-10, International Conference on Solid-State Devices and Materials - SSDM, 7/10/2009, p.1040-1041Publication Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs
Proceedings paper2005, Technical Digest International Electronic Devices Meeting - IEDM, 5/12/2005, p.36-5-1-36-5-4Publication Drift mobile and Hall scattering factors of holes in ultrathin Si1-xGex layers (0.3
Journal article2000, J. Appl. Physics, (88) 4, p.2016-2023Publication Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs
;Serra, N. ;Conzatti, F. ;Esseni, D. ;De Michielis, M. ;Palestri, P. ;Selmi, L. ;Thomas, S.Whall, T. E.Proceedings paper2009, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.71-74Publication First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling
Proceedings paper2008, Technical Digest International Electron Devices Meeting - IEDM, 15/12/2008, p.241-244Publication Gatestacks for scalable high-performance FinFETs
Proceedings paper2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.681-684Publication Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
Proceedings paper2007, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2007, p.110-111Publication Improved fin width scaling in fully-depleted FinFETs
;Duffy, Ray; ; ; ; Rooyackers, RitaProceedings paper2008, 38th European Sooid-State Device Research Conference - ESSDERC, 16/09/2008, p.334-337Publication Introducing novel metal gate materials for decananometer CMOS in the agile fab: a case study
Proceedings paper2004, Proceedings of the International Symposium on Semiconductor Manufacturing - ISSM, 27/09/2004, p.53-56Publication Ion implantation for low-resistive source/drain contacts in FinFET devices
Proceedings paper2008, Doping Engineering for Front-End Processing, 24/03/2008, p.1070-E02-01Publication Junction architecture for planar devices
Proceedings paper2007, Advanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS 3: New Materials, Processes and Equipment, 6/05/2007, p.351-364Publication Matching performance of FinFET devices with fin widths down to 10nm
Journal article2009, IEEE Electron Device Letters, (30) 12, p.1374-1376Publication Material aspects and challenges for SOI FinFET integration
Proceedings paper2008, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-based CMOS 4: New Materials, Processes, and Equipment, 18/05/2008, p.223-234