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Browsing by Author "Lander, Rob"

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    45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm

    Henson, Kirklen
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    Lander, Rob
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    Demand, Marc  
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    Dachs, Charles
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    Kaczer, Ben  
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    Deweerd, Wim
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    Schram, Tom  
    Proceedings paper
    2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.851-854
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    A practical baseline process for advanced CMOS devices research

    Ponomarev, Youri
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    Loo, Josine
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    Rittersma, Chris
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    Lander, Rob
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    Hooker, Jacob
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    Doornbos, Gerben  
    Proceedings paper
    2003, Proceedings 33rd European Solid-State Device Research Conference - ESSDERC, 16/09/2003, p.27-30
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    Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges

    Veloso, Anabela  
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    Collaert, Nadine  
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    De Keersgieter, An  
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    Witters, Liesbeth  
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    Rooyackers, Rita
    Proceedings paper
    2009, Silicon-on-Insulator Technology and Devices 14, 24/05/2009, p.45-54
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    ALD deposition of high-k and metal gate stacks for advanced CMOS applications

    Heyns, Marc  
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    Beckx, Stephan  
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    Caymax, Matty  
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    Claes, Martine  
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    De Gendt, Stefan  
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    Degraeve, Robin  
    Proceedings paper
    2004, Atomic Layer Deposition Conference, 16/08/2004
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    Application of HCl etch in the production of novel devices

    Hikavyy, Andriy  
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    Rooyackers, Rita
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    Verheyen, Peter  
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    Vellianitis, Georgios  
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    Van Dal, Mark  
    Meeting abstract
    2008, 213th ECS Meeting, 18/05/2008, p.647
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    Application of HCl gas phase etch in the production of novel devices

    Hikavyy, Andriy  
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    Rooyackers, Rita
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    Verheyen, Peter  
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    Leys, Frederik
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    Vellianitis, Georgios  
    Proceedings paper
    2008-05, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS. 4: New Materials, Processes, and Equipment, 18/05/2008, p.329-335
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    Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices

    Pelaz, L.
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    Duffy, Ray
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    Aboy, M.
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    Marques, L.
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    Lopez, P.
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    Santos, I.
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    Pawlak, Bartek  
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    Van Dal, Mark  
    Proceedings paper
    2008, IEEE International Electron Devices Meeting - IEDM, 15/12/2008, p.535-538
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    Characteristics and integration challenges of FinFET-based devices for (Sub-)22nm technology nodes circuit applications

    Veloso, Anabela  
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    Van Dal, Mark  
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    Collaert, Nadine  
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    De Keersgieter, An  
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    Witters, Liesbeth  
    Proceedings paper
    2009-10, International Conference on Solid-State Devices and Materials - SSDM, 7/10/2009, p.1040-1041
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    Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

    Subramanian, Vaidy
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    Parvais, Bertrand  
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    Borremans, Jonathan
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    Mercha, Abdelkarim  
    Proceedings paper
    2005, Technical Digest International Electronic Devices Meeting - IEDM, 5/12/2005, p.36-5-1-36-5-4
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    Drift mobile and Hall scattering factors of holes in ultrathin Si1-xGex layers (0.3

    Lander, Rob
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    Ponomarev, Youri
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    van Berkum, J. G. M.
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    de Boer, W. B.
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    Loo, Roger  
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    Caymax, Matty  
    Journal article
    2000, J. Appl. Physics, (88) 4, p.2016-2023
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    Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs

    Serra, N.
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    Conzatti, F.
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    Esseni, D.
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    De Michielis, M.
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    Palestri, P.
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    Selmi, L.
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    Thomas, S.
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    Whall, T. E.
    Proceedings paper
    2009, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.71-74
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    First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

    Merelle, Thomas
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    Curatola, Gilberto
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    Nackaerts, Axel
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    Collaert, Nadine  
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    Van Dal, Mark  
    Proceedings paper
    2008, Technical Digest International Electron Devices Meeting - IEDM, 15/12/2008, p.241-244
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    Gatestacks for scalable high-performance FinFETs

    Vellianitis, Georgios  
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    Van Dal, Mark  
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    Witters, Liesbeth  
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    Curatola, Gilberto
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    Doornbos, Gerben  
    Proceedings paper
    2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.681-684
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    Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

    Van Dal, Mark  
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    Collaert, Nadine  
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    Doornbos, Gerben  
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    Vellianitis, Georgios  
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    Curatola, Gilberto
    Proceedings paper
    2007, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2007, p.110-111
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    Improved fin width scaling in fully-depleted FinFETs

    Duffy, Ray
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    Van Dal, Mark  
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    Pawlak, Bartek  
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    Collaert, Nadine  
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    Witters, Liesbeth  
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    Rooyackers, Rita
    Proceedings paper
    2008, 38th European Sooid-State Device Research Conference - ESSDERC, 16/09/2008, p.334-337
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    Introducing novel metal gate materials for decananometer CMOS in the agile fab: a case study

    Deweerd, Wim
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    Schram, Tom  
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    Catana, Gabriela
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    Shamiryan, Denis
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    Garaud, Sylvain
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    Hellin, David  
    Proceedings paper
    2004, Proceedings of the International Symposium on Semiconductor Manufacturing - ISSM, 27/09/2004, p.53-56
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    Ion implantation for low-resistive source/drain contacts in FinFET devices

    Van Dal, Mark  
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    Duffy, Ray
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    Pawlak, Bartek  
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    Collaert, Nadine  
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    Jurczak, Gosia  
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    Lander, Rob
    Proceedings paper
    2008, Doping Engineering for Front-End Processing, 24/03/2008, p.1070-E02-01
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    Junction architecture for planar devices

    Pawlak, Bartek  
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    Duffy, R.
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    Hoffmann, Thomas Y.
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    Severi, Simone  
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    Felch, S.B.
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    Eyben, Pierre  
    Proceedings paper
    2007, Advanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS 3: New Materials, Processes and Equipment, 6/05/2007, p.351-364
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    Matching performance of FinFET devices with fin widths down to 10nm

    Magnone, Paolo
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    Mercha, Abdelkarim  
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    Subramanian, Vaidy
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    Parvais, Bertrand  
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    Collaert, Nadine  
    Journal article
    2009, IEEE Electron Device Letters, (30) 12, p.1374-1376
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    Material aspects and challenges for SOI FinFET integration

    Van Dal, Mark  
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    Vellianitis, Georgios  
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    Duffy, Ray
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    Doornbos, Gerben  
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    Pawlak, Bartek  
    Proceedings paper
    2008, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-based CMOS 4: New Materials, Processes, and Equipment, 18/05/2008, p.223-234
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