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Browsing by Author "Loo, Roger"

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    15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Loo, Roger  
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    Lee, Seung Hun
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    Sun, J.W.
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    Franco, Jacopo  
    Proceedings paper
    2014, Symposium on VLSI Technology, 9/06/2014, p.138-139
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    1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Hellings, Geert  
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    Krom, Raymond
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    Franco, Jacopo  
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    Eneman, Geert  
    Proceedings paper
    2011, Symposium on VLSI Technology, 13/06/2011, p.134-135
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    200mm CVD grown Si/SiGe resonant interband tunnel diodes optimized for high peak-to-valley current ratios

    Ramesh, Anisha
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    Berger, Paul
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    Douhard, Bastien  
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    Vandervorst, Wilfried  
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    Loo, Roger  
    Meeting abstract
    2012-06, 6th International Silicon Technology and Device Meeting, 4/06/2012, p.106-107
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    200mm Si/SiGe resonant interband tunneling diodes incorporating delta-doping layers grown by CVD

    Park, Si-Young
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    Anisha, R.
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    Berger, Paul
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    Loo, Roger  
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    Nguyen, Duy
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    Takeuchi, Shotaro
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    Caymax, Matty  
    Meeting abstract
    2009, Abstracts 6th International Conference on Silicon Epitaxy and Heterostructures - ICSI-6, 17/05/2009, p.72-73
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    25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions

    Verheyen, Peter  
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    Collaert, Nadine  
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    Rooyackers, Rita
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    Loo, Roger  
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    Shamiryan, Denis
    Proceedings paper
    2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.194-195
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    3D-DRAM Si/SiGe superlattices: inspection strategies and evaluation

    Beggiato, Matteo  
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    Loo, Roger  
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    Wei, S.
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    Moussa, Alain  
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    Bast, G.
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    Fukaya, K.
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    Cerbu, Dorin  
    Proceedings paper
    2025, 2025 Conference on Metrology Inspection and Process Control-Annual, 2025-02-24, p.1342612-1
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    50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells

    Collaert, Nadine  
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    Verheyen, Peter  
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    De Meyer, Kristin  
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    Loo, Roger  
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    Caymax, Matty  
    Proceedings paper
    2002, VLSI Nanoelectronics Workshop, 9/06/2002, p.15-16
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    50Gb/s C-band GeSi waveguide electro-absorption modulator

    Srinivasan, Ashwyn  
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    Verheyen, Peter  
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    Loo, Roger  
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    De Wolf, Ingrid  
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    Pantouvaki, Marianna  
    Proceedings paper
    2016, Optical Fiber Communications Conference - OFC, 20/03/2016, p.Tu3D.7
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    60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator

    Srinivasan, Ashwyn  
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    Porret, Clément  
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    Balakrishnan, Sadhishkumar  
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    Ban, Yoojin  
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    Loo, Roger  
    Proceedings paper
    2021, Optical Fiber Communications Conference and Exhibition (OFC), JUN 06-11, 2021
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    64 Gb/s O-Band GeSi Quantum-Confined Stark Effect Electro-Absorption Modulators Integrated in a 300 mm Silicon Photonics Platform

    Kandeel, Ahmed  
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    Hiblot, Gaspard  
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    Porret, Clement
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    Srinivasan, Srinivasan Ashwyn
    Journal article
    2025-MAR 15, JOURNAL OF LIGHTWAVE TECHNOLOGY, (43) 6, p.2794-2802
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    85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Eneman, Geert  
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    Hellings, Geert  
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    Pantisano, Luigi
    Proceedings paper
    2012, Symposium on VLSI Technology - VLSIT, 12/06/2012, p.163-164
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    8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

    Witters, Liesbeth  
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    Takeoka, Shinji
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    Yamaguchi, Shinpei
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    Hikavyy, Andriy  
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    Shamiryan, Denis
    Proceedings paper
    2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182
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    A 0.35µm BiCMOS process with selective epitaxial SiGe bipolar transistors

    Kuhn, Rudiger
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    Decoutere, Stefaan  
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    Caymax, Matty  
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    Vleugels, Frank  
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    Verschooten, Eric
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    Loo, Roger  
    Proceedings paper
    1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.436-439
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    A 0.35μm SiGe BiCMOS process featuring a 80 GHz Fmax HBT and integrated high-Q RF passive components

    Decoutere, Stefaan  
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    Vleugels, Frank  
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    Kuhn, Rudiger
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    Loo, Roger  
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    Caymax, Matty  
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    Jenei, Snezana
    Proceedings paper
    2000, Proceedings Bipolar/BiCMOS Circuits and Technology Meeting - BCTM, 24/09/2000, p.106-109
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    A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Sasaki, Yuichiro
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    Arimura, Hiroaki  
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    Schulze, Andreas
    Proceedings paper
    2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35
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    A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric

    Verheyen, Peter  
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    Collaert, Nadine  
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    Caymax, Matty  
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    Loo, Roger  
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    Van Rossum, Marc
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    De Meyer, Kristin  
    Proceedings paper
    2001, International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 18/04/2001, p.15-18
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    A 50nm high-k poly silicon gate stack with a buried SiGe channel

    Jakschik, S.
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    Hoffmann, Thomas Y.
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    Cho, Hag-Ju
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    Veloso, Anabela  
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    Loo, Roger  
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    Hyun, S.
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    Sorada, H.
    Proceedings paper
    2007, International Symposium on VLSI Technology, Systems and Applications, 23/04/2007
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    A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications

    Verheyen, Peter  
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    Collaert, Nadine  
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    Caymax, Matty  
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    Loo, Roger  
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    De Meyer, Kristin  
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    Van Rossum, Marc
    Proceedings paper
    1999, Silicon Nanoelectronics Workshop Abstracts, 12/06/1999
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    A demonstration of donor passivation through direct formation of V-Asx complexes in GexSn1-x

    Khanam, Afrina
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    Vohra, Anurag  
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    Slotte, Jonatan
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    Makkonen, Ilja
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    Loo, Roger  
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    Pourtois, Geoffrey  
    Journal article
    2020-05, Journal of Applied Physics, (127) 19, p.195703
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    A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)

    Wang, Gang
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    Loo, Roger  
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    Simoen, Eddy  
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    Souriau, Laurent  
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    Caymax, Matty  
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    Heyns, Marc  
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    Blanpain, Bart
    Journal article
    2009-03, Applied Physics Letters, (94) 10, p.102115
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