Browsing by Author "Martino, Joao"
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Publication Analog design with Line-TFET device experimental data: from device to circuit level
Journal article2020, Semiconductor Science and Technology, (35) 5, p.055025-1-055025-10Publication Channel length influence on the low-frequency noise of strained 45o rotated triple gate SOI nFinFETs
Proceedings paper2014, 10th Workshop on the Thematic Network on Silicon on Insulator Technology, Devices and Circuits - EUROSOI, 29/01/2014, p.1-2Publication Comparative study of vertical GAA TFETs and GAA MOSFETs in function of the inversion coefficient
Proceedings paper2016, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 25/01/2016, p.P11Publication Comparison between experimental and simulated strain profiles in Ge channels with embedded source/drain stressors
Journal article2014, Physica Status Solidi C, (11) 11_12, p.1578-1582Publication Comparison between experimental and simulated strain profiles in Ge channels with embedded source/drain stressors
Meeting abstract2014, E-MRS Spring Meeting Symposium X: Materials Research for Group IV Semiconductors, 16/05/2014Publication Detailed analysis of transport properties of FinFETs through Y-function method: effects of substrate orientation and strain
Proceedings paper2015, 30th Symposium on Microelectronics Technology and Devices - SBMICRO, 31/08/2015, p.1-4Publication Device-based threading dislocation assessment in germanium hetero-epitaxy
Proceedings paper2019, SBMICRO 2019, 26/08/2019Publication Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
Journal article2015, Solid-State Electronics, 103, p.209-215Publication Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature
Proceedings paper2014, 9th International Caribbean Conference on Devices, Circuits and Systems - ICCDCS, 2/04/2014, p.78-81Publication Experimental analysis of differential pairs designed with line tunnel FET devices
Proceedings paper2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.16.2Publication Field effect transistors: From MOSFET to tunnel-FET analog performance perspective
Proceedings paper2014, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology - ICSICT, 28/10/2014, p.674-677Publication Fin dimension influence on mechanical stressors in triple-gate SOI nMOSFETs
Proceedings paper2013, Advanced Semiconductor-on-Insulator Technology and Related Physics, 12/05/2013, p.187-192Publication Generation-recombination noise in advanced CMOS devices
Proceedings paper2016, 14th Symposium on High Purity and High Mobility Semiconductors, 2/10/2016, p.111-120Publication Ground plane impact on performance of relaxed Ge FinFETs
Journal article2019, Journal of Integrated Circuits and Systems, (14) 1, p.1-6Publication Ground plane influence on UTBB SOI nMOSFET analog parameters
Proceedings paper2015, 30th Symposium on Microelectronics Technology and Devices - SBMICRO 2015, 1/09/2015, p.1-4Publication Ground plane influence on zero-temperature-coefficient in SOI UTBB MOSFETs with different silicon film thicknesses
Proceedings paper2016, 31st Symposium on Microelectronics Technology and Devices - SBMICRO, 29/08/2016, p.1-4Publication Impact of the Zn diffusion process at the source side of a InXGa1-XAs nTFET on the analog parameters down to 10 K
Proceedings paper2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.8.2Publication Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications
Publication Influence of 45o substrate rotation on the analog performance of biaxially strained-silicon SOI MuGFETs
Proceedings paper2013, Advanced Semiconductor-on-Insulator Technology and Related Physics 16, 12/05/2013Publication Influence of high temperature on UTBB SOI nMOSFETs with and without ground plane
Proceedings paper2013, Advanced Semiconductor-on-Insulator Technology and Related Physics 16, 12/05/2013, p.85-91
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