Browsing by Author "Mocuta, Anda"
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Publication A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Proceedings paper2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35Publication A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Proceedings paper2015-06, IEEE Symposium on VLSI Technology, 15/06/2015, p.30-31Publication A new quality metric for III-V/high-k MOS gate stacks based on the frequency dispersion of accumulation capacitance and the CET
Journal article2017, IEEE Electron Device Letters, (38) 3, p.318-321Publication A TCAD low-field electron mobility model for thin-body InGaAs on InP MOSFETs calibrated to experimental characteristics
Journal article2015, IEEE Transactions on Electron Devices, (62) 11, p.3645-3652Publication Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.287-290Publication An analytical model of MOS admittance for border trap density extraction in high-k dielectrics of III-V MOS devices
Journal article2016, IEEE Transactions on Electron Devices, (63) 12, p.4707-4713Publication An in-depth study of high-performing strained germanium nanaowires pFETs
Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.83-84Publication Analysis of diffusion mechanisms for SSD in confined volumes : An alternative solution for extension formation in N7 and N5 technologies
Meeting abstract2018, E-MRS Spring Symposium I: Materials Research for Group IV Semiconductors: Growth, Characterization and Technological Development, 18/06/2018, p.I.15.5Publication Analytical model of thin-body InGaAs MOSFET low-field electron mobility for integration in TCAD models
Proceedings paper2015, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon - EUROSOI-ULIS, 26/01/2015, p.241-244Publication Assessment of SiGe quantum well transistors for DRAM peripheral applications
Proceedings paper2015, International Conference on IC Design and Technology - ICICDT, 1/06/2015, p.1-4Publication Backside power delivery as a scaling knob for future systems
Meeting abstract2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 25/02/2019, p.1096205Publication Band offsets in biaxially stressed SiGe layers for arbitrary orientations
Journal article2016, Journal of Applied Physics, (120) 5, p.54502Publication Band-to-band tunneling off-state leakage in Ge fins and nanowires: effect of quantum confinement
Proceedings paper2016, 21st International Conference on Simulation of Semiconductor Processes and Process - SISPAD, 06/09/2016, p.27-30Publication Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors
; ; ; ; Publication Calibration of the effective tunneling bandgap in GaAsSb/InGaAs for improved TFET performance prediction
Journal article2016, IEEE Transactions on Electron Devices, (63) 11, p.4248-4254Publication Calibration of the high-doping induced ballistic band-tails tunneling current in In0.53Ga0.47As Esaki diodes
Proceedings paper2017, Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop, 19/10/2017, p.1-3Publication CDM-time domain turn-on transient of ESD diodes in bulk FinFET and GAA NW technologies
; ; ; ; ; Meeting abstract2019, 2019 IEEE International Reliability Physics Symposium (IRPS), 31/03/2019, p.1-7Publication CFET standard-cell design down to 3Track height for node 3nm and below
Proceedings paper2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 24/02/2019, p.1096206Publication Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchup
Proceedings paper2018, Taiwan ESD and Reliability Conference, 7/09/2018Publication Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
Proceedings paper2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.159-162