Browsing by Author "Salahuddin, Shairfe Muhammad"

3D SRAM Macro Design in 3D Nanofabric Process Technology

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes

Buried Bitline for sub-5nm SRAM Design

Buried Interconnects for Sub-5 nm SRAM Design

Buried Power Rail Metal exploration towards the 1 nm Node

Buried power SRAM DTCO and system-level benchmarking in N3

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

From Design to System-Technology optimization for CMOS

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

SRAM with buried power distribution to improve write margin and performance in advanced technology nodes

System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs

Thermal stress-aware CMOS-SRAM partitioning in sequential 3-D technology

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations