Browsing by Author "Sisto, Giuliano"
- Results Per Page
- Sort Options
Publication 3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Proceedings paper2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020Publication Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
Proceedings paper2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021Publication Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)
Proceedings paper2021-11-04, 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP), NOV 04, 2021, p.17-23Publication Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs
Proceedings paper2023, IEEE International 3D Systems Integration Conference (3DIC), MAY 10-12, 2023Publication Design enablement of fine pitch face-to-face 3D system integration using die-by-die place & route
Proceedings paper2019, 2019 International 3D Systems Integration Conference - 3DIC, 8/10/2019, p.1-4Publication Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
; ; ; ; ; Proceedings paper2021, 5th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), APR 08-11, 2021Publication Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3 nm Era
Journal article2022, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (30) 10, p.1497-1506Publication Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization
Proceedings paper2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021Publication Fine-pitch 3D System Integration and Advanced CMOS nodes: Technology and System Design Perspective
Proceedings paper2021-02-22, Conference on Design-Process-Technology Co-optimization XV, FEB 22-26, 2021Publication GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Proceedings paper2024, 61st Design Automation Conference, JUN 23-27, 2024Publication IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and mu- & n- TSVs
; ; ; ; Proceedings paper2021, IEEE International Interconnect Technology Conference (IITC), JUL 06-09, 2021Publication Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network
; ; ; ; ; Proceedings paper2022, International Electron Devices Meeting (IEDM), DEC 03-07, 2022