Browsing by Author "Wu, Cheng-Wen"
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Publication Automated probe mark analysis
Proceedings paper2018-06, Semiconductor Wafer Test Workshop - SWTW, 3/06/2018Publication Automated Probe-Mark Analysis for Advanced Probe Technology Characterization
Journal article2021, IEEE DESIGN & TEST, (38) 5, p.82-89Publication DfT architecture for 3D-SICs with multiple towers
Proceedings paper2011-05, IEEE European Test Symposium - ETS, 23/05/2011, p.51-56Publication DfT architecture for multi-tower 3D-SICs
Oral presentation2011, DATE'11 Friday Workshop on "3D Integration"Publication Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages
Proceedings paper2023, IEEE International 3D Systems Integration Conference (3DIC), MAY 10-12, 2023Publication Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages
Proceedings paper2023, 41st IEEE VLSI Test Symposium (VTS), APR 24-26, 2023Publication Low-cost post-bond testing of 3D-ICs containing a passive silicon interposer base
Journal article2014-11, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (22) 11, p.2388-2401Publication Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base
Proceedings paper2011-11, IEEE Asian Test Symposium - ATS, 21/11/2011Publication Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base
Proceedings paper2011-09, IEEE International Test Conference - ITC, 20/09/2011, p.1-10Publication Solutions to multiple probing challenges for test access to multi-die stacked integrated circuits
; ; ; ; Publication Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults
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