Browsing by Author "Yamaguchi, Shinpei"
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Publication 1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
; ; ; ; Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.134-135Publication 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182Publication Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.654-657Publication Gate-last vs. gate-first technology for aggressively scaled EOT Logic/RF CMOS
Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.34-35Publication High performance Si.45Ge.55 implant free quantum well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.829-832Publication High-mobility 0.85nm-EOT Si0.45Ge0.55 pFETs: delivering high performance at scaled VDD
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.249-252Publication High-mobility Si1-xGex-channel PFETs: layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.41-42Publication Layout scaling of Si1-xGex pFETs
Journal article2011, IEEE Transactions on Electron Devices, (58) 8, p.2544-2550Publication Nano-beam diffraction investigation of the strain evolution in SiGe channel pFETs with gate first or gate last process
Oral presentation2012, 15th European Microscopy CongressPublication On the origin of mobility reduction in ultrathin EOT HK/MG CMOS devices: Impact from gate-stack and device architecture
Proceedings paper2011, International Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology - IWDTF-11, 20/01/2011, p.1-4Publication Si1-xGex-channel PFETs: scalability, layout considerations and compatibility with other stress techniques
Proceedings paper2011, Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3, 1/05/2011, p.493-503Publication Strain in PFETs analyzed by nano beam diffraction
Proceedings paper2010, International Microscopy Congress - IMC-17, 19/09/2010Publication Stress techniques in advanced transistor architectures: bulk FinFETs and implant-free quantum well transistors
Proceedings paper2012, Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufacturing -and- Tutorials in Nanotechnology, 6/05/2012, p.235-246