Browsing by author "Albert, Johan"
Now showing items 1-10 of 10
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15nm half-pitch patterning: EUV + SELF-aligned double patterning
Versluijs, Janko; Souriau, Laurent; Hellin, David; Orain, Isabelle; Kimura, Yoshie; Kunnen, Eddy; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Wiaux, Vincent; Xu, Kaidong (2012) -
15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU
Xu, Kaidong; Souriau, Laurent; Hellin, David; Versluijs, Janko; Wong, Patrick; Vangoidsenhoven, Diziana; Vandenbroeck, Nadia; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Tan, Chi Lim; Vertommen, Johan; Coenegrachts, Bart; Orain, I.; Kimura, Y.; Wiaux, Vincent; Boullart, Werner (2013) -
15nm HP patterning with EUV lithography and SADP
Souriau, Laurent; Hellin, David; Kunnen, Eddy; Versluijs, Janko; Dekkers, Harold; Albert, Johan; Orain, Isabelle; Yoshie, Kimura; Xu, Kaidong; Vertommen, Johan; Wiaux, Vincent; Boullart, Werner (2012) -
A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Aoulaiche, Marc; Cho, Moon Ju; Noh, Kyung Bong; Son, Yunik; Na, Hoon Jo; Kauerauf, Thomas; Douhard, Bastien; Nazir, Aftab; Chew, Soon Aik; Milenin, Alexey; Altamirano Sanchez, Efrain; Schoofs, Geert; Albert, Johan; Sebaai, Farid; Vecchio, Emma; Paraschiv, Vasile; Vandervorst, Wilfried; Lee, Sun Ghil; Collaert, Nadine; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014) -
A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Cho, Moon Ju; Simoen, Eddy; Aoulaiche, Marc; Albert, Johan; Chew, Soon Aik; Noh, Kyung Bong; Son, Yunik; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014) -
Cleaning and strip requirements for metal gate based CMOS integration
Schram, Tom; Sebaai, Farid; Claes, Martine; Vos, Rita; Wada, Masayuki; Albert, Johan; Rohr, Erika; Kubicek, Stefan (2009) -
Diffusion and gate replacement: a new gate-first high-k/metal gate CMOS integration scheme suppressing gate height symmetry
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Cho, Moon Ju; Simoen, Eddy; Aoulaiche, Marc; Albert, Johan; Chew, Soon Aik; Noh, Kyung Bong; Son, Yunik; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto; Fazan, Pierre; Thean, Aaron (2016) -
Guidelines for reducing NBTI based on its correlation with effective work function studied by CV-BTI on high-k first MOS capacitors with slant etched SiO2
Arimura, Hiroaki; Ragnarsson, Lars-Ake; Schram, Tom; Albert, Johan; Kaczer, Ben; Degraeve, Robin; Bury, Erik; Aoulaiche, Marc; Kauerauf, Thomas; Thean, Aaron; Horiguchi, Naoto; Groeseneken, Guido (2014) -
Implanted photoresist remover for advanced nodes including SiGe, Ge and high k-metals
Braun, S.; Vos, Rita; Klipp, Andreas; Claes, Martine; Bittner, Christian; Albert, Johan; Horiguchi, Naoto; Struyf, Herbert (2013) -
Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning
Xu, Kaidong; Souriau, Laurent; Hellin, David; Versluijs, Janko; Wong, Patrick; Vangoidsenhoven, Diziana; Vandenbroeck, Nadia; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Tan, Chi Lim; Vertommen, Johan; Coenegrachts, Bart; Orain, Isabelle; Kimura, Yoshie; Wiaux, Vincent; Boullart, Werner (2013-09)