Browsing by author "Chickermane, Vivek"

3D design-for-test architecture

Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03)

A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers

Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Hamdioui, Said; Marinissen, Erik Jan (2015)

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05)

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05)

At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs

Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-05)

At-speed inter-die interconnect test in 2.5D- and 3D-SICs

Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-10)

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

Shibin, Konstantin; Chickermane, Vivek; Keller, Brion; Papameletis, Christos; Marinissen, Erik Jan (2015-11)

Automated design-for-test for 2.5D and 3D SICs

Marinissen, Erik Jan; Konijnenburg, Mario; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Goel, Sandeep K. (2011-09)

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013-05)

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Papameletis, Christos; Keller, Brion; Chickermane, Vivek; Marinissen, Erik Jan; Hamdioui, Said (2013)

Automation of 3D DfT insertion and interconnect test generation

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011)

Automation of 3D-DfT insertion

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-11)

Automation of 3D-DfT insertion

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-09)

Automation of DfT insertion and interconnect test generation for 3D stacked ICs

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Konijnenburg, Mario; Marinissen, Erik Jan (2011-05)

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Sood, Navdeep; Marinissen, Erik Jan (2012-05)

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks

Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Sood, Navdeep; Goel, Sandeep K.; Chen, Ji-Jan; Mehta, Ashok; Lee, Frank; Marinissen, Erik Jan (2012-11)

DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K.; Marinissen, Erik Jan (2012-05)

Extension of a 3D-DfT architecture for embedded cores and multiple towers

Papameletis, Christos; Chickermane, Vivek; Keller, Brion; Marinissen, Erik Jan (2012)

Implementation aspects of a 3D DfT architecture

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan (2011)

Interconnect test for wide-IO memory-on-logic stacks

Marinissen, Erik Jan; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhashish; Sood, Navdeep (2012-07)