Browsing by author "Jang, Doyoung"
Now showing items 21-40 of 58
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Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies
Rawat, Amita; Sharan, Neha; Jang, Doyoung; Chiarella, Thomas; Bufler, Fabian; Catthoor, Francky; Parvais, Bertrand; Ganguly, Udayan (2021) -
Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires
Garcia Bardon, Marie; Sherazi, Yasser; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Debacker, Peter; Baert, Rogier; Mertens, Hans; Badaroglu, Mustafa; Mocuta, Anda; Horiguchi, Naoto; Mocuta, Dan; Raghavan, Praveen; Ryckaert, Julien; Verkest, Diederik; Steegen, An (2016) -
From Design to System-Technology optimization for CMOS
Ryckaert, Julien; Chehab, Bilal; Jang, Doyoung; Mirabelli, Gioele; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Zografos, Odysseas; Ahmed, Zubair; Weckx, Pieter; Hellings, Geert (2021) -
Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Veloso, Anabela; Matagne, Philippe; Jang, Doyoung; Huynh Bao, Trong; Vaisman Chasin, Adrian; Simoen, Eddy; Eneman, Geert; De Keersgieter, An; Mertens, Hans; Horiguchi, Naoto (2020) -
Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Veloso, Anabela; Matagne, Philippe; Jang, Doyoung; Huynh-Bao, Trong; Vaisman Chasin, Adrian; Simoen, Eddy; Eneman, Geert; De Keersgieter, An; Mertens, Hans; Horiguchi, Naoto (2020) -
Ge Devices: a potential candidate for sub-5nm nodes?
Sharan, Neha; Shaik, Khaja Ahmad; Jang, Doyoung; Schuddinck, Pieter; Yakimets, Dmitry; Garcia Bardon, Marie; Mitard, Jerome; Arimura, Hiroaki; Bufler, Fabian; Eneman, Geert; Collaert, Nadine; Parvais, Bertrand; Spessot, Alessio; Mocuta, Anda (2019) -
Holisitic device exploration for 7nm node
Raghavan, Praveen; Garcia Bardon, Marie; Jang, Doyoung; Schuddinck, Pieter; Yakimets, Dmitry; Ryckaert, Julien; Mercha, Abdelkarim; Horiguchi, Naoto; Collaert, Nadine; Mocuta, Anda; Mocuta, Dan; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Steegen, An (2015) -
Impact of fin shape variability on device performance towards 10nm node
Tomida, Kazuyuki; Hiraga, Keizo; Dehan, Morin; Hellings, Geert; Jang, Doyoung; Miyaguchi, Kenichi; Chiarella, Thomas; Kim, Min-Soo; Mocuta, Anda; Horiguchi, Naoto; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron (2015) -
Interconnect Design-Technology Co-Optimization for Sub-3nm Technology Nodes
Baert, Rogier; Ciofi, Ivan; Patli, Sudhir; Zografos, Odysseas; Sarkar, Satadru; Chehab, Bilal; Jang, Doyoung; Spessot, Alessio; Ryckaert, Julien; Tokei, Zsolt (2020) -
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Ahmed, Zubair; Afzalian, Aryan; Schram, Tom; Jang, Doyoung; Verreck, Devin; Smets, Quentin; Schuddinck, Pieter; Chehab, Bilal; Sutar, Surajit; Arutchelvan, Goutham; Soussou, Assawer; Asselberghs, Inge; Spessot, Alessio; Radu, Iuliana; Parvais, Bertrand; Ryckaert, Julien; Na, Myung Hee (2020) -
Lateral NWFET optimization for beyond 7nm nodes
Yakimets, Dmitry; Jang, Doyoung; Raghavan, Praveen; Eneman, Geert; Mertens, Hans; Schuddinck, Pieter; Mallik, Arindam; Garcia Bardon, Marie; Collaert, Nadine; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; De Meyer, Kristin (2015) -
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
Garcia Bardon, Marie; Moroz, Victor; Eneman, Geert; Schuddinck, Pieter; Dehan, Morin; Yakimets, Dmitry; Jang, Doyoung; Van der Plas, Geert; Mercha, Abdelkarim; Thean, Aaron; Verkest, Diederik; Steegen, An (2013) -
Limitations on lateral nanowire scaling beyond 7nm node
Kumar Das, Uttam; Garcia Bardon, Marie; Jang, Doyoung; Eneman, Geert; Schuddinck, Pieter; Yakimets, Dmitry; Raghavan, Praveen; Groeseneken, Guido (2017) -
Low frequency noise in single GaAsSb nanowires with self-induced compositional gradients
Huh, Junghwan; Kim, Dong-Chul; Munshi, A Mazid; Dheeraj, Dasa L; Jang, Doyoung; Kim, Gyu-Tae; Fimland, Bjĝrn-Ove; Weman, Helge (2016) -
Mobility analysis of surface roughness scattering in FinFET devices
Lee, Jae Woo; Jang, Doyoung; Mouis, Mireille; Kim, Gyu Tae; Chiarella, Thomas; Hoffmann, Thomas Y.; Ghibaudo, Gérard (2011) -
Monte Carlo comparison of n-type and p-type nanosheets with FinFETs: Effect of the number of sheets
Bufler, Fabian; Jang, Doyoung; Hellings, Geert; Eneman, Geert; Matagne, Philippe; Spessot, Alessio; Na, Myung Hee (2020) -
Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling
Veloso, Anabela; Eneman, Geert; De Keersgieter, An; Jang, Doyoung; Mertens, Hans; Matagne, Philippe; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
NANOWIRE & NANOSHEET FETS FOR ADVANCED ULTRA-SCALED, HIGH-DENSITY LOGIC AND MEMORY APPLICATIONS
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Jang, Doyoung; Huynh-Bao, T.; Vaisman Chasin, Adrian; Simoen, Eddy; De Keersgieter, An; Horiguchi, Naoto (2020) -
Nanowire & nanosheet FETs for ultra-scaled, hgh-density logic and memory applications
Veloso, Anabela; Huynh Bao, Trong; Matagne, Philippe; Jang, Doyoung; Eneman, Geert; Horiguchi, Naoto; Ryckaert, Julien (2020) -
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
Veloso, Anabela; Huynh Bao, Trong; Matagne, Philippe; Jang, Doyoung; Horiguchi, Naoto; Ryckaert, Julien; Mocuta, Dan (2019)