Browsing by author "Dangol, Anish"
Now showing items 1-15 of 15
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12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019) -
FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)
Tao, Zheng; Li, Waikin; Kim, Min-Soo; Devriendt, Katia; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Matagne, Philippe; Ragnarsson, Lars-Ake; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Altamirano Sanchez, Efrain; Lee, James; Li, YiSuo; Kanazawa, Kenichi; Harada, Nozomu; Masuoka, Fujio (2019) -
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Chew, Soon Aik; De Keersgieter, An; Mannaert, Geert; Rosseel, Erik; Schram, Tom; Devriendt, Katia; Tsvetanova, Diana; Dekkers, Harold; Demuynck, Steven; Vaisman Chasin, Adrian; Van Besien, Els; Dangol, Anish; Godny, Stephane; Douhard, Bastien; Bosman, Niels; Richard, Olivier; Geypen, Jef; Bender, Hugo; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto; Thean, Aaron (2016) -
Gate-all-around transistors based on vertically stacked Si nanowires
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Schram, Tom; Kunnen, Eddy; Ragnarsson, Lars-Ake; Dekkers, Harold; Hopf, Toby; Devriendt, Katia; Tsvetanova, Diana; Chew, Soon Aik; Kikuchi, Yoshiaki; Van Besien, Els; Rosseel, Erik; Mannaert, Geert; De Keersgieter, An; Vaisman Chasin, Adrian; Kubicek, Stefan; Dangol, Anish; Demuynck, Steven; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017) -
Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devies for (sub-)22nm nodes
Veloso, Anabela; Boccardi, Guillaume; Ragnarsson, Lars-Ake; Higuchi, Yuichi; Lee, Jae Won; Simoen, Eddy; Roussel, Philippe; Cho, Moon Ju; Chew, Soon Aik; Schram, Tom; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Brus, Stephan; Dangol, Anish; Paraschiv, Vasile; Vecchio, Emma; Shi, Xiaoping; Sebaai, Farid; Kellens, Kristof; Heylen, Nancy; Devriendt, Katia; Richard, Olivier; Bender, Hugo; Chiarella, Thomas; Arimura, Hiroaki; Thean, Aaron; Horiguchi, Naoto (2013) -
Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps
Lesniewska, Alicja; Varela Pedreira, Olalla; Lofrano, Melina; Murdoch, Gayle; van der Veen, Marleen; Dangol, Anish; Horiguchi, Naoto; Tokei, Zsolt; Croes, Kristof (2021) -
Reliability of Barrierless PVD Mo
Tierno, Davide; Hosseini, Maryam; van der Veen, Marleen; Dangol, Anish; Croes, Kristof; Demuynck, Steven; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
Replacement metal contact using sacrificial ILD0 for wrap around contact in scaled FinFET technology
Chew, Soon Aik; Demuynck, Steven; Zhang, Liping; Pacco, Antoine; Devriendt, Katia; Teugels, Lieve; Hopf, Toby; Versluijs, Janko; Vrancken, Christa; Dangol, Anish; Altamirano Sanchez, Efrain; Mocuta, Dan; Horiguchi, Naoto (2018) -
Si-cap-free SiGe p-channel Fin FETS and gate-all-around transistors in a replacement metal gate Process: interface trap density reduction and performance improvement by high-pressure deuterium anneal
Mertens, Hans; Ritzenthaler, Romain; Arimura, Hiroaki; Franco, Jacopo; Sebaai, Farid; Hikavyy, Andriy; Pawlak, Bartek; Machkaoutsan, Vladimir; Devriendt, Katia; Tsvetanova, Diana; Milenin, Alexey; Witters, Liesbeth; Dangol, Anish; Vancoille, Eric; Bender, Hugo; Badaroglu, Mustafa; Holsteyns, Frank; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto; Thean, Aaron (2015) -
Thermal and SF6-plasma treatments for improved (sub-)1nm EOT planar and FinFET-based RMG high-k last devices and enabling a simplified scalable CMOS integration scheme
Veloso, Anabela; Boccardi, Guillaume; Ragnarsson, Lars-Ake; Higuchi, Yuichi; Arimura, Hiroaki; Lee, Jae Woo; Simoen, Eddy; Cho, Moon Ju; Roussel, Philippe; Paraschiv, Vasile; Shi, Xiaoping; Schram, Tom; Chew, Soon Aik; Brus, Stephan; Dangol, Anish; Vecchio, Emma; Sebaai, Farid; Kellens, Kristof; Heylen, Nancy; Devriendt, Katia; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Conard, Thierry; Vaesen, Inge; Richard, Olivier; Bender, Hugo; Athimulam, Raja; Chiarella, Thomas; Thean, Aaron; Horiguchi, Naoto (2013) -
TiN/TaN selective etch in replacement metal gate with chlorine based plasmas
Tao, Zheng; Paraschiv, Vasile; Dekkers, Harold; Dangol, Anish; soon aik, chew (2014) -
Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal
Chew, Soon Aik; Yu, Hao; Schaekers, Marc; Demuynck, Steven; Mannaert, Geert; Kunnen, Eddy; Rosseel, Erik; Hikavyy, Andriy; Dangol, Anish; De Meyer, Kristin; Mocuta, Dan; Horiguchi, Naoto; Leusink, Gert; Wajda, Cory; Hakamata, T; Hasegawa, T; Tapily, K; Clark, R (2017) -
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Mertens, Hans; Ritzenthaler, Romain; Vaisman Chasin, Adrian; Schram, Tom; Kunnen, Eddy; Hikavyy, Andriy; Ragnarsson, Lars-Ake; Dekkers, Harold; Hopf, Toby; Wostyn, Kurt; Devriendt, Katia; Chew, Soon Aik; Kim, Min-Soo; Kikuchi, Yoshiaki; Rosseel, Erik; Mannaert, Geert; Kubicek, Stefan; Demuynck, Steven; Dangol, Anish; Bosman, Niels; Geypen, Jef; Carolan, Patrick; Bender, Hugo; Barla, Kathy; Horiguchi, Naoto; Mocuta, Dan (2016-12) -
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Ritzenthaler, Romain; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Vaisman Chasin, Adrian; Kenis, Karine; Devriendt, Katia; Mannaert, Geert; Dekkers, Harold; Dangol, Anish; Lin, Yongjin; Sun, Shiyu; Chen, Zhebo; Kim, Myungsun; Chen, ShiChung; Machillot, Jerome; Mitard, Jerome; Yoshida, Naomi; Kim, Namsung; Mocuta, Dan; Horiguchi, Naoto (2018) -
Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Mertens, Hans; Ritzenthaler, Romain; Pena, Vanessa; Santoro, Gaetano; Kenis, Karine; Schulze, Andreas; Dentoni Litta, Eugenio; Chew, Soon Aik; Devriendt, Katia; Chiarella, Thomas; Demuynck, Steven; Yakimets, Dmitry; Jang, Doyoung; Spessot, Alessio; Eneman, Geert; Dangol, Anish; Lagrain, Pieter; Bender, Hugo; Sun, Shiyu; Korolik, Michael; Kioussis, D.; Kim, Myungsun; Bu, Kyung-Ho; Chen, Shih Chung; Cogorno, Matt; Devrajan, J.; Machillot, Jerome; Yoshida, Naomi; Kim, Namsung; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017)