Browsing by author "Baert, Rogier"
Now showing items 1-20 of 49
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3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020) -
5nm: has the time for a device change come?
Raghavan, Praveen; Garcia Bardon, Marie; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Baert, Rogier; Debacker, Peter; Verkest, Diederik; Thean, Aaron (2016) -
An automatic scratch pad memory management tool and MPEG-4 encoder case study
Baert, Rogier; De Greef, Eddy; Brockmeyer, Erik; Vanmeerbeeck, Geert; Avasare, Prabhat; Mignolet, Jean-Yves; Cupak, Miroslav (2008) -
Application of cell-aware test on an advanced 3nm CMOS technology library
Gao, Zhan; Hu, Min-Chun; Baert, Rogier; Chehab, Bilal; Malagi, Santosh; Swenton, Joe; Huisken, Jos; Goossens, Kees; Marinissen, Erik Jan (2019-11) -
Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm
Prasad, D.; Nibhanupudi, S.; Das, S.; Zografos, Odysseas; Chehab, Bilal; Sarkar, Satadru; Baert, Rogier; Robinson, A.; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Kulkarni, J.; Cline, B.; Sinha, S. (2019) -
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology
Gao, Zhan; Hu, Min-Chun; Baert, Rogier; Chehab, Bilal; Swenton, Joe; Malagi, Santosh; Huisken, Jos; Goossens, Kees; Marinissen, Erik Jan (2024) -
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Huynh Bao, Trong; Yakimets, Dmitry; Ryckaert, Julien; Ciofi, Ivan; Baert, Rogier; Veloso, Anabela; Boemmels, Juergen; Collaert, Nadine; Roussel, Philippe; Demuynck, Steven; Raghavan, Praveen; Mercha, Abdelkarim; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2014-09) -
Circuit delay and power benchmark of graphene against Cu interconnects
Contino, Antonino; Ciofi, Ivan; Baert, Rogier; Wu, Xiangyu; Asselberghs, Inge; Celano, Umberto; Wilson, Chris; Tokei, Zsolt; Groeseneken, Guido; Soree, Bart (2019) -
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Design space exploration tool flow for MPSoC embedded design
Avasare, Prabhat; Couvreur, Chantal; Vanmeerbeeck, Geert; De Greef, Eddy; Ashby, Tom; Baert, Rogier; Wuyts, Roel; Stahl, Richard; D'Hondt, Maja; Rynders, Luc; Nollet, Vincent (2010) -
Design technology co-optimization for N10
Ryckaert, Julien; Raghavan, Praveen; Baert, Rogier; Garcia Bardon, Marie; Dusa, Mircea; Mallik, Arindam; Sakhare, Sushil; Vandewalle, Boris; Wambacq, Piet; Chava, Bharani; Croes, Kris; Dehan, Morin; Jang, Doyoung; Leray, Philippe; Liu, Tsung-Te; Miyaguchi, Kenichi; Parvais, Bertrand; Schuddinck, Pieter; Weemaes, Philippe; Mercha, Abdelkarim; Boemmels, Juergen; Horiguchi, Naoto; McIntyre, Greg; Thean, Aaron; Tokei, Zsolt; Cheng, Shaunee; Verkest, Diederik; Steegen, An (2014) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
Dynamic runtime task assignment
Blanch, Carolina; Baert, Rogier; D'Hondt, Maja (2011-04) -
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, Sushil; Perumkunnil, Manu; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Crotti, Davide; Yasin, Farrukh; Couet, Sebastien; Swerts, Johan; Kundu, Shreya; Yakimets, Dmitry; Baert, Rogier; Oh, Hyungrock; Spessot, Alessio; Mocuta, Anda; Kar, Gouri Sankar; Furnemont, Arnaud (2018) -
Enabling sub-5nm CMOS technology scaling thinner and taller!
Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019) -
Exploring parallelizations of applications for MPSoC platforms using MPA
Baert, Rogier; Brockmeyer, Erik; Wuytack, Sven; Ashby, Tom (2009) -
Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires
Garcia Bardon, Marie; Sherazi, Yasser; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Debacker, Peter; Baert, Rogier; Mertens, Hans; Badaroglu, Mustafa; Mocuta, Anda; Horiguchi, Naoto; Mocuta, Dan; Raghavan, Praveen; Ryckaert, Julien; Verkest, Diederik; Steegen, An (2016) -
Fast simulation of power electronic systems by partitioning, segmentation and caching
Baert, Rogier; Badaroglu, Mustafa; Mizutani, Kenji; Ueno, Hiroaki; Kudoh, Yuji; Nagai, Shuichi; Otsuka, Nobuyuki; Ueda, Daisuke (2012)