Browsing by author "Sakhare, Sushil"
Now showing items 1-19 of 19
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A comparative analysis on the impact of bank contention in STT-MRAM and SRAM based LLCs
Evenblij, Timon; Perumkunnil, Manu; Catthoor, Francky; Sakhare, Sushil; Debacker, Peter; Kar, Gouri Sankar; Furnemont, Arnaud; Bueno, Nicolas; Gomez-Perez, Ignacio; Tenllado, Christian (2019) -
A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs
Huynh Bao, Trong; Sakhare, Sushil; Yakimets, Dmitry; Ryckaert, Julien; Thean, Aaron; Mercha, Abdelkarim; Verkest, Diederik; Wambacq, Piet (2016) -
Cross-layer design and analysis of al ow power, high density STT-MRAM for embedded systems
Perumkunnil, Manu; Sakhare, Sushil; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Tenllado, Christian; Gomez, Jose Ignacio; Kar, Gouri Sankar; Furnemont, Arnaud; Catthoor, Francky (2017) -
Design technology co-optimization for a robust 10nm solution for logic design and Sram
Vandewalle, Boris; Chava, Bharani; Sakhare, Sushil; Ryckaert, Julien; Dusa, Mircea (2014) -
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
Huynh Bao, Trong; Sakhare, Sushil; Ryckaert, Julien; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2015) -
Design technology co-optimization for N10
Ryckaert, Julien; Raghavan, Praveen; Baert, Rogier; Garcia Bardon, Marie; Dusa, Mircea; Mallik, Arindam; Sakhare, Sushil; Vandewalle, Boris; Wambacq, Piet; Chava, Bharani; Croes, Kris; Dehan, Morin; Jang, Doyoung; Leray, Philippe; Liu, Tsung-Te; Miyaguchi, Kenichi; Parvais, Bertrand; Schuddinck, Pieter; Weemaes, Philippe; Mercha, Abdelkarim; Boemmels, Juergen; Horiguchi, Naoto; McIntyre, Greg; Thean, Aaron; Tokei, Zsolt; Cheng, Shaunee; Verkest, Diederik; Steegen, An (2014) -
Distinctive behavior of perpendicular magnetic tunnel junctions with size comparable to the electrical switching nucleation
Kim, Woojin; Rao, Siddharth; Van Beek, Simon; Garello, Kevin; Couet, Sebastien; Swerts, Johan; Mertens, Sofie; Lin, Tsann; Souriau, Laurent; Kundu, Shreya; Tsvetanova, Diana; Donadio, Gabriele Luca; Yasin, Farrukh; Sakhare, Sushil; Furnemont, Arnaud; Kar, Gouri Sankar (2017) -
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, Sushil; Perumkunnil, Manu; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Crotti, Davide; Yasin, Farrukh; Couet, Sebastien; Swerts, Johan; Kundu, Shreya; Yakimets, Dmitry; Baert, Rogier; Oh, Hyungrock; Spessot, Alessio; Mocuta, Anda; Kar, Gouri Sankar; Furnemont, Arnaud (2018) -
Impact of interconnect multiple-patterning variability on SRAMs
Karageorgos, Ioannis; Dehaene, Wim; Stucchi, Michele; Raghavan, Praveen; Ryckaert, Julien; Tokei, Zsolt; Verkest, Diederik; Baert, Rogier; Sakhare, Sushil (2015) -
JSWof 5.5 MA/cm2 and RA of 5.2- $X $lm2 STT-MRAM technology for LLC application
Sakhare, Sushil; Rao, Siddharth; Perumkunnil, Manu; Couet, Sebastien; Crotti, Davide; Van Beek, Simon; Furnemont, Arnaud; Catthoor, Francky; Kar, Gouri Sankar (2020) -
Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
Sakhare, Sushil; Trivkovic, Darko; Mountsier, Tom; Kim, Min-Soo; Mocuta, Dan; Ryckaert, Julien; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Dusa, Mircea (2015) -
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
Perumkunnil, Manu; Oh, Hyungrock; Hartmann, Matthias; Sakhare, Sushil; Tenllado, Christian; Ignacio Gomez, Jose; Kar, Gouri Sankar; Furnemont, Arnaud; Catthoor, Francky; Senni, Sophiane; Novo, David; Gamatie, Abdoulaye; Torres, Lionel (2018) -
Simplistic simulation-based device-VT-targeting technique to determine technology high-density LELE-gate-patterned FinFET SRAM in sub-10 nm era
Sakhare, Sushil; Miyaguchi, Kenichi; Raghavan, Praveen; Mercha, Abdelkarim (2015) -
Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks
Swerts, Johan; Liu, Enlong; Couet, Sebastien; Mertens, Sofie; Rao, Siddharth; Kim, Woojin; Garello, Kevin; Souriau, Laurent; Kundu, Shreya; Crotti, Davide; Yasin, Farrukh; Jossart, Nico; Sakhare, Sushil; Devolder, Thibaut; Van Beek, Simon; O'Sullivan, Barry; Van Elshocht, Sven; Furnemont, Arnaud; Kar, Gouri Sankar (2017) -
SRAM designs for 5nm node and beyond: opportunities and challenges
Huynh Bao, Trong; Sakhare, Sushil; Ryckaert, Julien; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Switching characteristics of perpendicular magnetic tunnel junction with various sizes
Kim, Woojin; Rao, Siddharth; Van Beek, Simon; Garello, Kevin; Couet, Sebastien; Swerts, Johan; Mertens, Sofie; Lin, Tsann; Souriau, Laurent; Kundu, Shreya; Tsvetanova, Diana; Crotti, Davide; Donadio, Gabriele Luca; Yasin, Farrukh; Sakhare, Sushil; Furnemont, Arnaud; Kar, Gouri Sankar (2016) -
Thermal stability and switching performance metrics of top-pinned STT-MRAM devices with CMOS-compatible dual MgO MTJ stacks
Rao, Siddharth; Kim, Woojin; Couet, Sebastien; Swerts, Johan; Mertens, Sofie; Lin, Tsann; Souriau, Laurent; Kundu, Shreya; Tsvetanova, Diana; Crotti, Davide; Yasin, Farrukh; Sakhare, Sushil; Furnemont, Arnaud; Kar, Gouri Sankar (2017) -
Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
Huynh Bao, Trong; Ryckaert, Julien; Sakhare, Sushil; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2016) -
Vertical device architecture for 5nm and beyond: device & circuit implications
Thean, Aaron; Yakimets, Dmitry; Huynh Bao, Trong; Schuddinck, Pieter; Sakhare, Sushil; Garcia Bardon, Marie; Sibaja-Hernandez, Arturo; Ciofi, Ivan; Eneman, Geert; Veloso, Anabela; Ryckaert, Julien; Raghavan, Praveen; Mercha, Abdelkarim; Mocuta, Anda; Tokei, Zsolt; Verkest, Diederik; Wambacq, Piet; De Meyer, Kristin; Collaert, Nadine (2015)