Browsing by author "Hikavyy, Andriy"
Now showing items 1-20 of 293
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15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Mitard, Jerome; Witters, Liesbeth; Loo, Roger; Lee, Seung Hun; Sun, J.W.; Franco, Jacopo; Ragnarsson, Lars-Ake; Brand, A.; Lu, X.; Yoshido, N.; Eneman, Geert; Brunco, David; Vorderwestner, M.; Storck, P.; Milenin, Alexey; Hikavyy, Andriy; Waldron, Niamh; Favia, Paola; Vanhaeren, Danielle; Vanderheyden, Annelies; Richard, Olivier; Mertens, Hans; Arimura, Hiroaki; Sioncke, Sonja; Vrancken, Christa; Bender, Hugo; Eyben, Pierre; Barla, Kathy; Lee, Sun Ghil; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron (2014) -
1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
Mitard, Jerome; Witters, Liesbeth; Hellings, Geert; Krom, Raymond; Franco, Jacopo; Eneman, Geert; Hikavyy, Andriy; Vincent, Benjamin; Loo, Roger; Favia, Paola; Dekkers, Harold; Altamirano Sanchez, Efrain; Vanderheyden, Annelies; Vanhaeren, Danielle; Eyben, Pierre; Takeoka, Shinji; Yamaguchi, Shinpei; Van Dal, Mark; Wang, Wei-E; Hong, Sug-Hun; Vandervorst, Wilfried; De Meyer, Kristin; Biesemans, Serge; Absil, Philippe; Horiguchi, Naoto; Hoffmann, Thomas Y. (2011) -
3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Besnard, Guillaume; Radu, Ionut; Vandooren, Anne; Wu, Zhicheng; Franco, Jacopo; Li, Waikin; Arimura, Hiroaki; Mannaert, Geert; Rosseel, Erik; Hikavyy, Andriy; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018-11) -
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018) -
85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
Mitard, Jerome; Witters, Liesbeth; Eneman, Geert; Hellings, Geert; Pantisano, Luigi; Hikavyy, Andriy; Loo, Roger; Eyben, Pierre; Horiguchi, Naoto; Thean, Aaron (2012) -
8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Witters, Liesbeth; Takeoka, Shinji; Yamaguchi, Shinpei; Hikavyy, Andriy; Shamiryan, Denis; Cho, Moon Ju; Chiarella, Thomas; Ragnarsson, Lars-Ake; Loo, Roger; Kerner, Christoph; Crabbe, Yvo; Franco, Jacopo; Tseng, Joshua; Wang, Wei-E; Rohr, Erika; Schram, Tom; Richard, Olivier; Bender, Hugo; Biesemans, Serge; Absil, Philippe; Hoffmann, Thomas Y. (2010) -
A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06) -
A new complementary hetero-junction vertical tunnel-FET integration scheme
Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Walke, A.; Devriendt, Katia; Locorotondo, Sabrina; Demand, Marc; Bryce, George; Loo, Roger; Hikavyy, Andriy; Vandeweyer, Tom; Huyghebaert, Cedric; Collaert, Nadine; Thean, Aaron (2013) -
A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks
Porret, Clément; Vohra, Anurag; Sebaai, Farid; Douhard, Bastien; Hikavyy, Andriy; Loo, Roger (2018) -
Ab initio analysis of defect formation and dopant activation in P and As co-doped Si
Nakazaki, Nobuya; Rosseel, Erik; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Horiguchi, Naoto; Pourtois, Geoffrey (2019) -
Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
Arimura, Hiroaki; Eneman, Geert; Capogreco, Elena; Witters, Liesbeth; De Keersgieter, An; Favia, Paola; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Bender, Hugo; Ragnarsson, Lars-Ake; Mitard, Jerome; Collaert, Nadine; Mocuta, Dan; Horiguchi, Naoto (2018) -
An in-depth study of high-performing strained germanium nanaowires pFETs
Mitard, Jerome; Jang, Doyoung; Eneman, Geert; Arimura, Hiroaki; Parvais, Bertrand; Richard, Olivier; Van Marcke, Patricia; Witters, Liesbeth; Capogreco, Elena; Bender, Hugo; Ritzenthaler, Romain; Mertens, Hans; Hikavyy, Andriy; Loo, Roger; Dekkers, Harold; Sebaai, Farid; Horiguchi, Naoto; Mocuta, Anda; Collaert, Nadine (2018) -
An investigation of disilane-digermane precursors combination for low temperature SiGe epitaxy
Hikavyy, Andriy; Zyulkov, Ivan; Loo, Roger (2015) -
An investigation of growth and properties of Si capping layers used in advanced SiGe/Ge based pMOS transistors
Hikavyy, Andriy; Witters, Liesbeth; Mitard, Jerome; Vanherle, Wendy; Vandervorst, Wilfried; Dekoster, Johan; Loo, Roger; Caymax, Matty (2012) -
Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions
Bargallo Gonzalez, Mireia; Thomas, Nicole; Simoen, Eddy; Verheyen, Peter; Hikavyy, Andriy; Leys, Frederik; Okuno, Yasutoshi; Vissouvanadin Soubaretty, Bertrand; Van Daele, Benny; Geenen, Luc; Loo, Roger; Claeys, Cor; Machkaoutsan, Vladimir; Tomasini, P.; Thomas, S.G.; Lu, J.P.; Weijtmans, J.W.; Wise, R. (2007) -
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs
Vandooren, Anne; Rooyackers, Rita; Leonelli, Daniele; Hikavyy, Andriy; Devriendt, Katia; Demand, Marc; Loo, Roger; Groeseneken, Guido; Huyghebaert, Cedric (2013) -
Application of Cl2 for low temperature etch and epitaxy
Hikavyy, Andriy; Porret, Clément; Rosseel, Erik; Loo, Roger (2018) -
Application of Cl2 for low temperature etch and epitaxy
Hikavyy, Andriy; Porret, Clément; Rosseel, Erik; Milenin, Alexey; Loo, Roger (2019)