Browsing by author "Chiarella, Thomas"
Now showing items 21-40 of 130
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Channel hot carrier degradation mechanism in long/short channel n-FinFETs
Cho, Moon Ju; Roussel, Philippe; Kaczer, Ben; Degraeve, Robin; Franco, Jacopo; Aoulaiche, Marc; Chiarella, Thomas; Kauerauf, Thomas; Horiguchi, Naoto; Groeseneken, Guido (2013) -
Charge based DC compact modeling of bulk FinFET transistor
Cerdeira, Antonio; Garduno, Ivan; Tinoco, Julio; Ritzenthaler, Romain; Franco, Jacopo; Togo, Mitsuhiro; Chiarella, Thomas; Claeys, Cor (2013) -
CMOS integration of dual work function phase controlled Ni FUSI with simultaneous integration of nMOS (NiSi) and pMOS (Ni-rich silicide) gates on HfSiON
Lauwers, Anne; Veloso, Anabela; Hoffmann, Thomas Y.; Van Dal, Mark; Vrancken, Christa; Brus, Stephan; Locorotondo, Sabrina; de Marneffe, Jean-Francois; Sijmus, Bram; Kubicek, Stefan; Chiarella, Thomas; Kmieciak, Malgorzata; Opsomer, Karl; Niwa, Masaaki; Mitsuhashi, Riichirou; Kottantharayil, Anil; Yu, HongYu; Demeurisse, Caroline; Verbeeck, Rita; de Potter de ten Broeck, Muriel; Absil, Philippe; Maex, Karen; Jurczak, Gosia; Biesemans, Serge; Kittl, Jorge (2005-12) -
Combining TCAD and advanced metrology techniques to support device integration towards N3
Eyben, Pierre; De Keersgieter, An; Celano, Umberto; Wouters, Lennaert; Chiarella, Thomas; Ritzenthaler, Romain; Mertens, Hans; Richard, Olivier; Paredis, Kristof; Matagne, Philippe; Mitard, Jerome; Horiguchi, Naoto; Goux, Ludovic (2021) -
Comparison of temperature dependent carrier transport in FinFET and gate-all-Around nanowire FET
Kim, Soohyun; Kim, Jungchun; Jang, Doyoung; Ritzenthaler, Romain; Parvais, Bertrand; Mitard, Jerome; Mertens, Hans; Chiarella, Thomas; Horiguchi, Naoto; Lee, Jae Woo (2020) -
Complete extraction of defect bands responsible for instabilities in n and pFinFETs
Rzepa, Gerhard; Waltl, Michael; Goes, Wolfgang; Kaczer, Ben; Franco, Jacopo; Chiarella, Thomas; Horiguchi, Naoto; Grasser, Tibor (2016) -
Deposition of HfO2 on germanium and the impact of surface pretreatments
Van Elshocht, Sven; Brijs, Bert; Caymax, Matty; Conard, Thierry; Chiarella, Thomas; De Gendt, Stefan; De Jaeger, Brice; Kubicek, Stefan; Meuris, Marc; Onsia, Bart; Richard, Olivier; Teerlinck, Ivo; Van Steenbergen, Jan; Zhao, Chao; Heyns, Marc (2004) -
Device scaling model for bulk FinFETs
Medury, Aditya; Mercha, Abdelkarim; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Collaert, Nadine; Bhat, N; Bhat, KN (2012) -
Dopant and carrier profiling for 3D-device architectures
Mody, Jay; Kambham, Ajay Kumar; Zschaetzsch, Gerd; Chiarella, Thomas; Collaert, Nadine; Witters, Liesbeth; Eyben, Pierre; Gilbert, Matthieu; Koelling, Sebastian; Schulze, Andreas; Hoffmann, Thomas Y.; Vandervorst, Wilfried (2011) -
Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution
Mody, Jay; Kambham, Ajay Kumar; Zschaetzsch, Gerd; Schatzer, Philipp; Chiarella, Thomas; Collaert, Nadine; Witters, Liesbeth; Jurczak, Gosia; Horiguchi, Naoto; Gilbert, Matthieu; Eyben, Pierre; Koelling, Sebastian; Schulze, Andreas; Hoffmann, Thomas Y.; Vandervorst, Wilfried (2010) -
Effect of sub-10nm fin-widths on the analog performance of FinFETs
Bhoir, Mandar; Nihar, Mohapatra; Chiarella, Thomas; Ragnarsson, Lars-Ake; Mitard, Jerome; Terzieva, Valentina; Horiguchi, Naoto (2019) -
Efficient physical defect model applied to PBTI in high-k stacks
Rzepa, G.; Franco, Jacopo; Subirats, Alexandre; Jech, M.; Vaisman Chasin, Adrian; Grill, A.; Waltl, M.; Knobloch, T.; Stampfer, B.; Chiarella, Thomas; Horiguchi, Naoto; Ragnarsson, Lars-Ake; Linten, Dimitri; Grasser, T.; Kaczer, Ben (2017) -
Electrical characteristics of P-type bulk Si fin field-effect transistor using solid-source doping with 1-nm phosphosilicate glass
Kikuchi, Yoshiaki; Chiarella, Thomas; De Roest, David; Blanquart, Timothee; De Keersgieter, An; Kenis, Karine; Peter, Antony; Ong, Patrick; Van Besien, Els; Tao, Zheng; Kim, Min-Soo; Kubicek, Stefan; Chew, Soon Aik; Schram, Tom; Demuynck, Steven; Mocuta, Anda; Mocuta, Dan; Horiguchi, Naoto (2016) -
Electrode process dependent NBTI chracteristics of TiN gate FinFETs
Kim, Jinju; Cho, Moon Ju; Pantisano, Luigi; Chiarella, Thomas; Togo, Mitsuhiro; Horiguchi, Naoto; Groeseneken, Guido; Lee, ByoungHun (2012-04) -
ESD diodes in next generation bulk FinFET and GAA NW technology nodes
Chen, Shih-Hung; Hellings, Geert; Linten, Dimitri; Mertens, Hans; Chiarella, Thomas; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto (2018) -
ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy
Chen, Wen-Chieh; Chen, Shih-Hung; Chiarella, Thomas; Hellings, Geert; Linten, Dimitri; Groeseneken, Guido (2022) -
Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies
Rawat, Amita; Sharan, Neha; Jang, Doyoung; Chiarella, Thomas; Bufler, Fabian; Catthoor, Francky; Parvais, Bertrand; Ganguly, Udayan (2021) -
Extraction of the random component of time-dependent variability using matched pairs
Kaczer, Ben; Franco, Jacopo; Roussel, Philippe; Groeseneken, Guido; Chiarella, Thomas; Horiguchi, Naoto; Grasser, Tibor (2015) -
Fast ramped voltage characterization of single trap bias and temperature impact on time-dependent VTH variability
Toledano Luque, Maria; Degraeve, Robin; Roussel, Philippe; Ragnarsson, Lars-Ake; Chiarella, Thomas; Horiguchi, Naoto; Mocuta, Anda; Thean, Aaron (2014-09) -
FinFETs and their futures
Horiguchi, Naoto; Parvais, Bertrand; Chiarella, Thomas; Collaert, Nadine; Veloso, Anabela; Rooyackers, Rita; Verheyen, Peter; Witters, Liesbeth; Redolfi, Augusto; De Keersgieter, An; Brus, Stephan; Zschaetzsch, Gerd; Ercken, Monique; Altamirano Sanchez, Efrain; Locorotondo, Sabrina; Demand, Marc; Jurczak, Gosia; Vandervorst, Wilfried; Hoffmann, Thomas Y.; Biesemans, Serge (2011)