Browsing by author "Tao, Zheng"
Now showing items 21-40 of 49
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EUV extendibility via dry development rinse process
Sayan, Safak; Tao, Zheng; De Simone, Danilo; Vandenberghe, Geert (2016) -
FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3
Tao, Zheng; Zhang, Liping; Dupuy, Emmanuel; Chan, BT; Altamirano Sanchez, Efrain; Lazzarino, Frederic (2020) -
FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)
Tao, Zheng; Li, Waikin; Kim, Min-Soo; Devriendt, Katia; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Matagne, Philippe; Ragnarsson, Lars-Ake; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Altamirano Sanchez, Efrain; Lee, James; Li, YiSuo; Kanazawa, Kenichi; Harada, Nozomu; Masuoka, Fujio (2019) -
Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
Mertens, Hans; Ritzenthaler, Romain; Oniki, Yusuke; Briggs, Basoene; Chan, BT; Hikavyy, Andriy; Hopf, Toby; Mannaert, Geert; Tao, Zheng; Sebaai, Farid; Peter, Antony; Vandersmissen, Kevin; Dupuy, Emmanuel; Rosseel, Erik; Batuk, Dmitry; Geypen, Jef; Martinez Alanis, Gerardo Tadeo; Abigail, Daniel_; Grieten, Eva; D'have, Koen; Mitard, Jerome; Subramanian, Sujith; Ragnarsson, Lars-Ake; Weckx, Pieter; Chehab, Bilal; Hellings, Geert; Ryckaert, Julien; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Chew, Soon Aik; De Keersgieter, An; Mannaert, Geert; Rosseel, Erik; Schram, Tom; Devriendt, Katia; Tsvetanova, Diana; Dekkers, Harold; Demuynck, Steven; Vaisman Chasin, Adrian; Van Besien, Els; Dangol, Anish; Godny, Stephane; Douhard, Bastien; Bosman, Niels; Richard, Olivier; Geypen, Jef; Bender, Hugo; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto; Thean, Aaron (2016) -
Gate-all-around NWFETs vs. triple-gate FinFETs: junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS
Veloso, Anabela; Hellings, Geert; Cho, Moon Ju; Simoen, Eddy; Devriendt, Katia; Paraschiv, Vasile; Vecchio, Emma; Tao, Zheng; Versluijs, Janko; Souriau, Laurent; Dekkers, Harold; Brus, Stephan; Geypen, Jef; Lagrain, Pieter; Bender, Hugo; Eneman, Geert; Matagne, Philippe; De Keersgieter, An; Fang, W.; Collaert, Nadine; Thean, Aaron (2015) -
Gate-all-around transistors based on vertically stacked Si nanowires
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Schram, Tom; Kunnen, Eddy; Ragnarsson, Lars-Ake; Dekkers, Harold; Hopf, Toby; Devriendt, Katia; Tsvetanova, Diana; Chew, Soon Aik; Kikuchi, Yoshiaki; Van Besien, Els; Rosseel, Erik; Mannaert, Geert; De Keersgieter, An; Vaisman Chasin, Adrian; Kubicek, Stefan; Dangol, Anish; Demuynck, Steven; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017) -
Gate-First High-k/Metal Gate FinFET for advanced DRAM peripheral transistors
Dupuy, Emmanuel; Capogreco, Elena; Dentoni Litta, Eugenio; Tao, Zheng; Sebaai, Farid; Spessot, Alessio; Horiguchi, Naoto (2022-09-20) -
Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation
Kikuchi, Yoshiaki; Hopf, Toby; Mannaert, Geert; Tao, Zheng; Waite, A.; Cournoyer, J.; Borniquel, J.; Schreutelkamp, Rob; Ritzenthaler, Romain; Kim, Min-Soo; Kubicek, Stefan; Chew, Soon Aik; Devriendt, Katia; Schram, Tom; Demuynck, Steven; Variam, N.; Horiguchi, Naoto; Mocuta, Dan (2016) -
Improving pH sensing by nanoscaling the width of CMOS technology compatible FinFETs
Gupta, Mihir; Veloso, Anabela; Tao, Zheng; Li, Waikin; Peumans, Peter; Van Roy, Wim; Martens, Koen; Lagae, Liesbet (2017) -
In depth analysis of 3D NAND enablers in gate stack integration and demonstration in 3D devices
Tan, Chi Lim; Lavizzari, Simone; Blomme, Pieter; Breuil, Laurent; Vecchio, Emma; Sebaai, Farid; Paraschiv, Vasile; Tao, Zheng; Schepers, Bart; Nyns, Laura; Peter, Antony; Dekkers, Harold; Ong, Patrick; Tsvetanova, Diana; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Raymaekers, Tom; Jossart, Nico; Mennella, Pasquale; Delhougne, Romain; Vadakupudhu Palayam, Senthil; Arreghini, Antonio; Van den Bosch, Geert; Furnemont, Arnaud (2017) -
Interconnects for scaled SRAM with vertical Surrounded Gate Transistors (SGT)
Boemmels, Juergen; Harada, N.; Kim, Min-Soo; Mitard, Jerome; Kikuchi, Yoshiaki; Li, Waikin; Tao, Zheng; Puliyalil, Harinarayanan; Devriendt, Katia; Lorant, Christophe; Le, Quoc Toan; Kesters, Els; Jourdan, Nicolas; El-Mekki, Zaid; Teugels, Lieve; van der Veen, Marleen; Li, Y.; Nakamura, H.; Mocuta, Dan; Masuoka, F. (2019) -
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Veloso, Anabela; Parvais, Bertrand; Matagne, Philippe; Simoen, Eddy; Huynh Bao, Trong; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Rosseel, Erik; Ercken, Monique; Chan, BT; Delvaux, Christie; Altamirano Sanchez, Efrain; Versluijs, Janko; Tao, Zheng; Suhard, Samuel; Brus, Stephan; Sibaja-Hernandez, Arturo; Waldron, Niamh; Lagrain, Pieter; Richard, Olivier; Bender, Hugo; Vaisman Chasin, Adrian; Kaczer, Ben; Ivanov, Tsvetan; Ramesh, Siva; De Meyer, Kristin; Ryckaert, Julien; Collaert, Nadine; Thean, Aaron (2016) -
Key challenges and opportunities for 3D sequential integration
Vandooren, Anne; Witters, Liesbeth; Franco, Jacopo; Mallik, Arindam; Parvais, Bertrand; Wu, Zhicheng; Li, Waikin; Rosseel, Erik; Hikavyy, Andriy; Peng, Lan; Rassoul, Nouredine; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Waldron, Niamh; Boemmels, Juergen; De Heyn, Vincent; Mocuta, Dan; Ryckaert, Julien; Collaert, Nadine (2018-10) -
N10 logic patterning
Xu, Kaidong; Tao, Zheng; Hody, Hubert; Mannaert, Geert; Kunnen, Eddy; Mao, Ming; Lazzarino, Frederic; Decoster, Stefan (2014) -
N10 SADP bulk FinFET depth micro loading improvement with bias pulsing plasma
Tao, Zheng; Vos, Ingrid; Altamirano Sanchez, Efrain; Xu, Kaidong; Hellin, David; Camerotto, Elisabeth; Jumel, Helene; Titus, Monica (2014) -
Nanoscale elastocapillary effect induced by thin-liquid-film instability
Vrancken, Nandi; Ghosh, Tanmay; Anand, Utkarsh; Aabdin, Zainul; Chee, See Wee; Baraissov, Zhaslan; Terryn, Herman; De Gendt, Stefan; Tao, Zheng; Xu, XiuMei; Holsteyns, Frank; Mirsaidov, Utkur (2020) -
Patterning challenges in advanced device architectures: FinFETs to nanowire
Horiguchi, Naoto; Milenin, Alexey; Tao, Zheng; Hody, Hubert; Altamirano Sanchez, Efrain; Veloso, Anabela; Witters, Liesbeth; Waldron, Niamh; Ragnarsson, Lars-Ake; Kim, Min-Soo; Kikuchi, Yoshiaki; Mertens, Hans; Raghavan, Praveen; Piumi, Daniele; Collaert, Nadine; Barla, Kathy; Thean, Aaron (2016) -
pH Sensing using nano-scaled CMOS compatible FinFETs
Gupta, Mihir; Veloso, Anabela; Tao, Zheng; Li, Waikin; Lagae, Liesbet; Martens, Koen; Van Roy, Wim (2018) -
Pillar patterning of Silicon / III-V vertical nanowire FET for 7nm node and beyond
Chan, BT; Tao, Zheng; Altamirano Sanchez, Efrain; Veloso, Anabela; de Marneffe, Jean-Francois; Singh, Arjun (2018)