1.2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates

Abstract

This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electron-mobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (V-th) of 3.2 V, an ON/OFF ratio of 108, low specific ON-resistance (R-on,R-sp) of 5.8 m Omega-cm(2) and hard breakdown voltage (V-bd) at 1800 V. Optimized devices also show good wafer scale uniformity ( sigma(Ron) =1.2% ) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.