Browsing by Author "Banerjee, Kaustuv"

A comprehensive variability study of doped HfO2 FeFET for memory applications

A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash

Analysis of Wake-Up Reversal Behavior Induced by Imprint in La:HZO MFM Capacitors

Antenna effect in 65nm NMOS devices with 9.5nm thick HfOx gate dielectric

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells

Capacitor-less, Long-Retention (> 400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

Comprehensive Investigation of Constant Voltage Stress Time-Dependent Breakdown and Cycle-to-Breakdown Reliability in Y-Doped and Si-Doped HfO2 Metal-Ferroelectric-Metal Memory

Controllable p-Type Doping of 2D WSe2 pFET by Engineered Surface Charge Transfer Doping With Metal Co-Seeding

Defect profiling in FEFET Si:HfO2 layers

Demonstration of 64 Conductance States and Large Dynamic Range in Sidoped HfO2 FeFETs under Neuromorphic Computing Operations

Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control

Electrical Investigation of Wake-Up in High Endurance Fatigue-Free La and Y Doped HZO Meal-Ferroelectric-Metal Capacitors

Elucidating possible crystallographic origins of wake-up mechanisms in ferroelectric hafnia

Endurance of ferroelectric La-doped HfO2 for SFS gate-stack memory devices

Engineering Strain and Texture in Ferroelectric Scandium-Doped Aluminium Nitride

Ferroelectric FET with Gd-doped HfO2: A Step Towards Better Uniformity and Improved Memory Performance

Ferroelectric La-Doped ZrO2/HfxZr1-xO2 Bilayer Stacks with Enhanced Endurance

Ferroelectric Switching in FEFET: Physics of the Atomic Mechanism and Switching Dynamics in HfZrOx, HfO2 with Oxygen Vacancies and Si dopants

First demonstration of ferroelectric Si:Hf0(2) based 3D FE-FET with trench architecture for dense non-volatile memory application

First demonstration of sub-12 nm gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices