Browsing by Author "Chickermane, Vivek"

3D design-for-test architecture

A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed inter-die interconnect test in 2.5D- and 3D-SICs

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

Automated design-for-test for 2.5D and 3D SICs

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Automation of 3D DfT insertion and interconnect test generation

Automation of 3D-DfT insertion

Automation of 3D-DfT insertion

Automation of DfT insertion and interconnect test generation for 3D stacked ICs

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks

DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

Extension of a 3D-DfT architecture for embedded cores and multiple towers

Implementation aspects of a 3D DfT architecture

Interconnect test for wide-IO memory-on-logic stacks