Browsing by Author "De Vos, Joeri"
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Publication 3D stacking induced mechanical stress effects
Proceedings paper2014, IEEE 64th Electronic Components and Technology Conference - ECTC, 27/05/2014, p.309-315Publication A complementary high-voltage technology based on n-type CdSe:In and p-type Ge:Cu thin film transistors
Journal article1996, IEEE Electron Device Letters, (17) 12, p.581-583Publication A fully planar stacked gate flash technology with T-shaped floating gate for increased cell coupling ratio
; ; ; ; ; Proceedings paper2007, Proceedings 2nd International Conference on Memory Technology and Design - ICMTD, 7/05/2007, p.243-245Publication A highly reliable 1.4μm pitch via-last TSV module for wafer-to-wafer hybrid bonded 3D-SOC systems
Proceedings paper2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 28/05/2019, p.1035-1040Publication A highly reliable 1×5μm via-last TSV module
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.94-96Publication A low-cost poly-sidewall erase HIMOSTM technology for 130-90nm embedded flash memories
Oral presentation2004, 20th IEEE Non-Volatile Semiconductor Memory Workshop - NVSMWPublication A new 2 isolated-bits/cell Flash memory device with self aligned split gate structure using ONO stacks for charge storage
Proceedings paper2003, 19th IEEE Nonvolatile Semiconductor Memory Workshop - NVSMW, 16/02/2003, p.46-47Publication A new scalable self-aligned dual-bit split-gate charge trapping memory device
Journal article2005, IEEE Trans. Electron Devices, (52) 10, p.2250-2257Publication A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage
; ; ; ; Publication A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
Proceedings paper2014, Electronics System-Integration Technology Conference - ESTC, 16/09/2014, p.1-5Publication A study on substrate noise coupling among TSVs in 3D chip stack
Journal article2018, IEICE Electronics Express, (15) 13, p.20180460Publication Accuracy in Infrared Overlay Metrology
Proceedings paper2026, 37th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2026-05-11, p.1-6Publication Advanced experimental Back-End-Of-Line (BEOL) stability test: measurements and simulations
Journal article2015, Microelectronic Engineering, (137) 2015, p.54-58Publication Advanced experimental BEOL stability test: measurements and simulations
Proceedings paper2014, Materials for Advanced Metallization Conference - MAM, 2/03/2013Publication Advances in SiCN-SiCN bonding with high accuracy wafer-to-wafer (W2W) stacking technology
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.985-992Publication An efficient bump pad design to mitigate the flip chip package induced stress
Proceedings paper2015, InterPACK & ICNNM, 6/07/2015, p.1-7Publication Anomalous C-V inversion in TSV's: The problem and its cure
; ; ; ; ; Journal article2018, IEEE Transactions on Electron Devices, (65) 4, p.1473-1479Publication Backside illuminated hybrid FPA achieving low cross-talk combined with high QE
Proceedings paper2011, International Image Sensor Workshop - IISW, 8/06/2011, p.P31Publication Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 12, p.7963-7969Publication Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding