Browsing by Author "Gupta, Anshul"

1/f noise in fully integrated electrolytically gated FinFETs with fin width down to 20nm

A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Airgap Integration in MP18 Two-Level Semi-damascene Interconnects with Fully Self-aligned Vias

Alternative metals: from ab initio screening to calibrated narrow line models

Buried Bitline for sub-5nm SRAM Design

Buried Interconnects for Sub-5 nm SRAM Design

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Buried power rail integration with FinFETs for ultimate CMOS scaling

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Buried Power Rail Metal exploration towards the 1 nm Node

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm

Buried power SRAM DTCO and system-level benchmarking in N3

Challenges with SOT-MRAM integration towards N5 node and beyond

Characterization and modeling of hot carrier degradation in N-channel gate-all-around nanowire FETs

CMOS area scaling and the need for high aspect ratio vias

Demonstration of MP18-26nm Ru Semi-Damascene Spacer-is-Dielectric SADP Integration

Device-, circuit- & block-level evaluation of CFET in a 4 track library

Direct metal nanowire patterning using ion beam etch

Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes