Browsing by Author "Kunnen, Eddy"
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Publication 15nm half-pitch patterning: EUV + SELF-aligned double patterning
Oral presentation2012, International Symposium on Extreme Ultraviolet Lithography - EUVLPublication 15nm HP patterning with EUV lithography and SADP
Meeting abstract2012, 34th International Symposium on Dry Process - DPS, 15/11/2012Publication 2D and 3D photoresist line roughness characterization
Journal article2013, Microelectronic Engineering, 110, p.100-107Publication 2D and 3D photoresist line roughness characterization
Oral presentation2012, 38th International Micro & Nano Engineering Conference - MNEPublication A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Proceedings paper2009, Nanotechnology Workshop, 13/06/2009Publication A novel fully self-aligned SiGe:C HBT architecture featuring a single step epitaxial collector-base process
Proceedings paper2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.655-658Publication A novel isolation scheme featuring cavities in the collector for a high-speed 0.13μm SiGe:C BiCMOS technology
Proceedings paper2007, Silicon Monolithic Integrated Circuits in RF Systems Topical Meeting, 10/01/2007, p.158-161Publication A way to integrate multiple block layers for middle of line contact patterning
Proceedings paper2015, Advanced Etch Technology for Nanopattering IV, 22/02/2015, p.94280WPublication Active species in porous media: random walk and capture in traps
Publication Active species in porous media: random walk and capture in traps
Publication BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
Proceedings paper2017, Silicon Nanoelectronics Workshop - SNW, 4/07/2017, p.139-140Publication CMOS patterning over high aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Proceedings paper2017, Advances in Patterning Materials and Processes XXXIV, 26/02/2017, p.1014618Publication CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Proceedings paper2017, Advances in Patterning Materials and Processes XXXIV, 26/02/2017, p.1014618Publication Contact module at dense gate pitch technology challenges
Proceedings paper2014, IEEE International Interconnect Technology Conference - IITC, 20/05/2014, p.307-310Publication Cu resistivity scaling limits for 20 nm copper damascene lines
Proceedings paper2007, IEEE International Interconnect Technology Conference - IITC, 4/06/2007, p.49-51Publication Demonstration of asymmetric gate-oxide thickness four-terminal FinFETs having flexible threshold voltage and good subthreshold slope
Journal article2007-03, IEEE Electron Device Letters, (28) 3, p.217-219Publication Development of 2-step plasma texturing process for crystalline silicon solar cells with Linear Microwave Plasma Sources (LPS)
Meeting abstract2011, 4th International Workshop Plasma Etch and Strip in Microelectronics - PESM, 5/05/2011Publication Development, optimization and evaluation of a CF4 pre-treatment process to remove unwanted interfacial layers in stacks of CVD and PECVD polycrystalline silicon-germanium for MEMS applications
Meeting abstract2010, 217th ECS Meeting, 25/04/2010, p.1817Publication Development, optimization and evaluation of a CF4 pretreatment process to remove unwanted interfacial layers in stacks of CVD and PECVD polycrystalline silicon-germanium for MEMS applications
Proceedings paper2010, Sensors, Actuators, and Microsystems (General), 25/04/2010, p.79-90Publication Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration
Proceedings paper2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.5.3