Browsing by Author "Lorenzini, Martino"
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Publication A new 2 isolated-bits/cell Flash memory device with self aligned split gate structure using ONO stacks for charge storage
Proceedings paper2003, 19th IEEE Nonvolatile Semiconductor Memory Workshop - NVSMW, 16/02/2003, p.46-47Publication A new scalable self-aligned dual-bit split-gate charge trapping memory device
Journal article2005, IEEE Trans. Electron Devices, (52) 10, p.2250-2257Publication Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
Proceedings paper2004, Electrical Overstress / Electrostatic Discharge Symposium Proceedings, 19/09/2004, p.2.B.1Publication Analysis and improved compact modelling of the breakdown behaviour of sub-0.25 micron ESD protection ggNMOS devices
Proceedings paper2001, Electrical Overstress/Electrostratic Discharge Syymposium Proceedings - EOS/ESD, 11/09/2001, p.461-468Publication Analytical model for failure rate prediction due to anomalous charge loss of Flash memories
Proceedings paper2001, IEDM Technical Digest, 2/12/2001, p.699-702Publication Analytical percolation model for predicting anomalous charge loss in flash memories
Journal article2004, IEEE Trans. Electron Devices, (51) 9, p.1392-1400Publication Back-bias enhanced source-side injection in 0.25μm embedded flash memories
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium., p.608-611Publication Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge pumping technique
Oral presentation2003, Non Volatile Memories With Discrete Storage Nodes WorkshopPublication Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique
Journal article2004-09, Solid-State Electronics, (48) 9, p.1525-1530Publication Comparative reliability investigation of different nitride based local charge trapping memory devices
Proceedings paper2005, Proceedings 43rd Annual International Reliability Physics Symposium, 17/04/2005, p.181-185Publication Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide
Proceedings paper2003, VLSI Technology Symposium, 10/06/2003, p.163-164Publication High-k materials for tunnel barrier engineering in future memory technologies
Meeting abstract2004-10, Extended Abstracts 206th Electrochemical Society Meeting, 3/10/2004, p.868Publication Higk-k materials for tunnel barrier engineering in floating-gate flash memories
Meeting abstract2005, Meeting Abstracts 208th Electrochemical Society, 1/10/2005Publication Integration of a composite SiO2HfO2 interpoly dielectric layer for low voltage polypoly erase in a 0.18μm HIMOSTM memory cell.
Oral presentation2004, 20th IEEE Non-Volatile Semiconductor Memory Workshop - NVSMWPublication Lateral distribution of electrons trapped in nitride layers
Proceedings paper2005, Materials and Processes for Nonvolatile Memories, 29/11/2004, p.D1.3Publication Performance and reliability of 0.35μm/0.25μm HIMOS® technology for embedded flash memory applications
Proceedings paper1999, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials - SSDM, 21/09/1999, p.538-539Publication Reliability investigation of a source side injection local charge trapping device
Oral presentation2004, 20th IEEE Non-Volatile Semiconductor Memory Workshop - NVSMWPublication Scaling effects in dual-bit split-gate memory devices
Journal article2005-11, Solid-State Electronics, (49) 11, p.1862-1866Publication Scaling effects in dual-bit split-gate nitride memory devices
Proceedings paper2005, International Conference on Memory Technology and Designs, 21/05/2005, p.227-230