Browsing by Author "Panarella, Luca"

Deep Understanding of Electron Beam Effects on 2D Layered Semiconducting Devices Under Bias Applications

Evidence of contact-induced variability in industrially-fabricated highly-scaled MoS2 FETs

Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs

Exploring manufacturability of novel 2D channel materials: 300 mm wafer-scale 2D NMOS & PMOS using MoS2, WS2, & WSe2

Gate oxide reliability: upcoming trends, challenges, and opportunities

Impact of doping and channel inhomogeneities on the stability of industrially fabricated WS2 FETs

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs

Implications of side contact depth on the Schottky barrier of 2D field-effect transistors

Improving IGZO transistor PBTI reliability with hydrogen anneal achieving overdrive voltage of 1.2V for a lifetime of 5 years at 95°C

Observation of fully recoverable leakage behaviour in HfO2 gate oxide of WS2 2D FETs induced by local mechanical stress

Positive Bias Temperature Instability (PBTI) in n-and p-channel polysilicon thin-film transistors (TFTs) for high-voltage applications

Predictive Reliability Modeling for NSFET Optimization-Part II: HCD and BTI

Process implications on the stability and reliability of 300 mm FAB MoS2 field-effect transistors

Selective etch process for fab-compatible top contacts, replacement oxide, and interlayer removal in 2D FETs

Terman method to study threshold voltage hysteresis of Si/SiGe heterostructures at cryogenic temperatures